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ports.h File Reference


Detailed Description

Ports & registers for the MC68HC(9)12B MCU.

The ports & registers in this header file were massaged from the "M68HC12B Family Technical Data M68HC12B/D Rev. 4, 4/2002" by Motorola, Inc. using pstotext and some serious vim regex's :-) Original filename was M68HC12B.pdf. All data was extracted from section 2.3, "Register Block", pp68. NB: Could not use new editions of this datasheet due to PDF encryption or other "feature" that prevented pstotext(1) from working.

Note:
#defines with _L/_H appended are manual edits to avoid duplicates
See also:
asm-m68hc12b/vectors.h

asm-m68hc12b/ports_def.h

Definition in file asm-m68hc12b/ports.h.

Go to the source code of this file.

Defines

#define PORTA   (*(volatile unsigned char *)0x0000) /* Port A Data Register pp131 bits: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Reset: U U U U U U U U */
#define PORTB   (*(volatile unsigned char *)0x0001) /* Port B Data Register pp133 bits: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Reset: U U U U U U U U */
#define DDRA   (*(volatile unsigned char *)0x0002) /* Data Direction Register A pp132 bits: DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Reset: 0 0 0 0 0 0 0 0 */
#define DDRB   (*(volatile unsigned char *)0x0003) /* Data Direction Register B pp134 bits: DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Reset: 0 0 0 0 0 0 0 0 */
#define PORTE   (*(volatile unsigned char *)0x0008) /* Port E Data Register pp135 bits: PE7 PE6 PE5 PD4 PD3 PD2 PD1 PD0 Reset: 0 0 0 0 0 0 0 0 */
#define DDRE   (*(volatile unsigned char *)0x0009) /* Data Direction Register E pp136 bits: DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 0 0 Reset: 0 0 0 0 1 0 0 0 */
#define PEAR   (*(volatile unsigned char *)0x000A) /* Port E Assignment Register pp137 bits: NDBE CGMTE PIPOE NECLK LSTRE RDWE 0 0 Reset: 1 0 0 1 0 0 0 0 */
#define MODE   (*(volatile unsigned char *)0x000B) /* Mode Register pp121 bits: SMODN MODB MODA ESTR IVIS EBSWAI 0 EME Reset: 0 0 0 1 1 0 0 1 */
#define PUCR   (*(volatile unsigned char *)0x000C) /* Pullup Control Register pp140 bits: 0 0 0 PUPE 0 0 PUPB PUPA Reset: 0 0 0 1 0 0 0 0 */
#define RDRIV   (*(volatile unsigned char *)0x000D) /* Reduced Drive Register pp141 bits: 0 0 0 0 RDPE 0 RDPB RDPA Reset: 0 0 0 0 0 0 0 0 */
#define INITRM   (*(volatile unsigned char *)0x0010) /* RAM Initialization Register pp124 bits: RAM15 RAM14 RAM13 RAM12 RAM11 0 0 0 Reset: 0 0 0 0 1 0 0 0 */
#define INITRG   (*(volatile unsigned char *)0x0011) /* Register Initialization Register pp123 bits: REG15 REG14 REG13 REG12 REG11 0 0 MMSWAI Reset: 0 0 0 0 0 0 0 0 */
#define INITEE   (*(volatile unsigned char *)0x0012) /* EEPROM Initialization Register pp125 bits: EE15 EE14 EE13 EE12 0 0 0 EEON Reset: 0 0 0 1 0 0 0 1 */
#define MISC   (*(volatile unsigned char *)0x0013) /* Miscellaneous Mapping Control Register pp126 bits: 0 NDRF RFSTR1 RFSTR0 EXSTR1 EXSTR0 MAPROM ROMON Reset: 0 0 0 0 0 0 0 0 */
#define RTICTL   (*(volatile unsigned char *)0x0014) /* Real­Time Interrupt Control Register pp180 bits: RTIE RSWAI RSBCK 0 RTBYP RTR2 RTR1 RTR0 Reset: 0 0 0 0 0 0 0 0 */
#define RTIFLG   (*(volatile unsigned char *)0x0015) /* Real­Time Interrupt Flag Register pp181 bits: RTIF 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define COPCTL   (*(volatile unsigned char *)0x0016) /* COP Control Register pp182 bits: CME FCME FCM FCOP DISR CR2 CR1 CR0 Reset: 0 0 0 0 0 0 0 1 */
#define COPRST   (*(volatile unsigned char *)0x0017) /* Arm/Reset COP Timer Register pp184 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define INTCR   (*(volatile unsigned char *)0x001E) /* Interrupt Control Register pp108 bits: IRQE IRQEN DLY 0 0 0 0 0 Reset: 0 1 1 0 0 0 0 0 */
#define HPRIO   (*(volatile unsigned char *)0x001F) /* Highest Priority I Interrupt Register pp109 bits: 1 1 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 Reset: 1 1 1 1 0 0 1 0 */
#define BRKCT0   (*(volatile unsigned char *)0x0020) /* Breakpoint Control Register 0 pp458 bits: BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define BRKCT1   (*(volatile unsigned char *)0x0021) /* Breakpoint Control Register 1 pp459 bits: 0 BKDBE BKMBH BKMBL BK1RWE BK1RW BK0RWE BK0RW Reset: 0 0 0 0 0 0 0 0 */
#define BRKAH   (*(volatile unsigned char *)0x0022) /* Breakpoint Address Register High pp461 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define BRKAL   (*(volatile unsigned char *)0x0023) /* Breakpoint Address Register Low pp462 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define BRKDH   (*(volatile unsigned char *)0x0024) /* Breakpoint Data Register High pp462 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define BRKDL   (*(volatile unsigned char *)0x0025) /* Breakpoint Data Register Low pp463 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWCLK   (*(volatile unsigned char *)0x0040) /* PWM Clocks and Concatenate Register pp193 bits: CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0 Reset: 0 0 0 0 0 0 0 0 */
#define PWPOL   (*(volatile unsigned char *)0x0041) /* PWM Clock Select and Polarity Register pp195 bits: PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0 Reset: 0 0 0 0 0 0 0 0 */
#define PWEN   (*(volatile unsigned char *)0x0042) /* PWM Enable Register pp197 bits: 0 0 0 0 PWEN3 PWEN2 PWEN1 PWEN0 Reset: 0 0 0 0 0 0 0 0 */
#define PWPRES   (*(volatile unsigned char *)0x0043) /* PWM Prescaler Counter Register pp198 bits: 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWSCAL0   (*(volatile unsigned char *)0x0044) /* PWM Scale Register 0 pp199 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWSCNT0   (*(volatile unsigned char *)0x0045) /* PWM Scale Counter Register 0 pp199 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWSCAL1   (*(volatile unsigned char *)0x0046) /* PWM Scale Register 1 pp200 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWSCNT1   (*(volatile unsigned char *)0x0047) /* PWM Scale Counter Register 1 pp200 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWCNT0   (*(volatile unsigned char *)0x0048) /* PWM Channel Counter Register 0 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWCNT1   (*(volatile unsigned char *)0x0049) /* PWM Channel Counter Register 1 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWCNT2   (*(volatile unsigned char *)0x004A) /* PWM Channel Counter Register 2 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWCNT3   (*(volatile unsigned char *)0x004B) /* PWM Channel Counter Register 3 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PWPER0   (*(volatile unsigned char *)0x004C) /* PWM Channel Period Register 0 pp202 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWPER1   (*(volatile unsigned char *)0x004D) /* PWM Channel Period Register 1 pp202 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWPER2   (*(volatile unsigned char *)0x004E) /* PWM Channel Period Register 2 pp203 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWPER3   (*(volatile unsigned char *)0x004F) /* PWM Channel Period Register 3 pp203 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWDTY0   (*(volatile unsigned char *)0x0050) /* PWM Channel Duty Register 0 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWDTY1   (*(volatile unsigned char *)0x0051) /* PWM Channel Duty Register 1 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWDTY2   (*(volatile unsigned char *)0x0052) /* PWM Channel Duty Register 2 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWDTY3   (*(volatile unsigned char *)0x0053) /* PWM Channel Duty Register 3 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define PWCTL   (*(volatile unsigned char *)0x0054) /* PWM Control Register pp206 bits: 0 0 0 PSWAI CENTR RDPP PUPP PSBCK Reset: 0 0 0 0 0 0 0 0 */
#define PWTST   (*(volatile unsigned char *)0x0055) /* PWM Special Mode Register pp207 bits: DISCR DISCP DISCAL 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define PORTP   (*(volatile unsigned char *)0x0056) /* Port P Data Register pp208 bits: PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 Reset: U U U U U U U U */
#define DDRP   (*(volatile unsigned char *)0x0057) /* Port P Data Direction Register pp208 bits: DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0 Reset: 0 0 0 0 0 0 0 0 */
#define ATDCTL0   (*(volatile unsigned char *)0x0060) /* ATD Control Register 0 pp422 bits: 0 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define ATDCTL1   (*(volatile unsigned char *)0x0061) /* ATD Control Register 1 pp422 bits: 0 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define ATDCTL2   (*(volatile unsigned char *)0x0062) /* ATD Control Register 2 pp423 bits: ADPU AFFC AWAI 0 0 0 ASCIE ASCIF Reset: 0 0 0 0 0 0 0 0 */
#define ATDCTL3   (*(volatile unsigned char *)0x0063) /* ATD Control Register 3 pp424 bits: 0 0 0 0 0 0 FRZ1 FRZ0 Reset: 0 0 0 0 0 0 0 0 */
#define ATDCTL4   (*(volatile unsigned char *)0x0064) /* ATD Control Register 4 pp425 bits: S10BM SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Reset: 0 0 0 0 0 0 0 1 */
#define ATDCTL5   (*(volatile unsigned char *)0x0065) /* ATD Control Register 5 pp427 bits: S8CM SCAN MULT CD CC CB CA Reset: 0 0 0 0 0 0 0 0 */
#define ATDSTAT_H   (*(volatile unsigned char *)0x0066) /* ATD Status Register pp429 bits: SCF 0 0 0 0 CC2 CC1 CC0 Reset: 0 0 0 0 0 0 0 0 */
#define ATDSTAT_L   (*(volatile unsigned char *)0x0067) /* ATD Status Register pp429 bits: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 Reset: 0 0 0 0 0 0 0 0 */
#define ATDTSTH   (*(volatile unsigned char *)0x0068) /* ATD Test Register High pp430 bits: SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 Reset: 0 0 0 0 0 0 0 0 */
#define ATDTSTL   (*(volatile unsigned char *)0x0069) /* ATD Test Register Low pp430 bits: SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 Reset: 0 0 0 0 0 0 0 0 */
#define PORTAD   (*(volatile unsigned char *)0x006F) /* Port AD Data Input Register pp431 bits: PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 Reset: After reset, reflect the state of the input pins */
#define ADRx0H   (*(volatile unsigned char *)0x0070) /* ATD Result Register 0 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx0L   (*(volatile unsigned char *)0x0071) /* ATD Result Register 0 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define ADRx1H   (*(volatile unsigned char *)0x0072) /* ATD Result Register 1 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx1L   (*(volatile unsigned char *)0x0073) /* ATD Result Register 1 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define ADRx2H   (*(volatile unsigned char *)0x0074) /* ATD Result Register 2 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx2L   (*(volatile unsigned char *)0x0075) /* ATD Result Register 2 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define ADRx3H   (*(volatile unsigned char *)0x0076) /* ATD Result Register 3 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx3L   (*(volatile unsigned char *)0x0077) /* ATD Result Register 3 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define ADRx4H   (*(volatile unsigned char *)0x0078) /* ATD Result Register 4 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx4L   (*(volatile unsigned char *)0x0079) /* ATD Result Register 4 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define ADRx5H   (*(volatile unsigned char *)0x007A) /* ATD Result Register 5 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx5L   (*(volatile unsigned char *)0x007B) /* ATD Result Register 5 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define ADRx6H   (*(volatile unsigned char *)0x007C) /* ATD Result Register 6 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx6L   (*(volatile unsigned char *)0x007D) /* ATD Result Register 6 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define ADRx7H   (*(volatile unsigned char *)0x007E) /* ATD Result Register 7 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
#define ADRx7L   (*(volatile unsigned char *)0x007F) /* ATD Result Register 7 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
#define TIOS   (*(volatile unsigned char *)0x0080) /* Timer IC/OC Select Register pp216 bits: IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 Reset: 0 0 0 0 0 0 0 0 */
#define CFORC   (*(volatile unsigned char *)0x0081) /* Timer Compare Force Register pp216 bits: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Reset: 0 0 0 0 0 0 0 0 */
#define OC7M   (*(volatile unsigned char *)0x0082) /* Timer Output Compare 7 Mask Register pp217 bits: OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 Reset: 0 0 0 0 0 0 0 0 */
#define OC7D   (*(volatile unsigned char *)0x0083) /* Timer Output Compare 7 Data Register pp217 bits: OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 Reset: 0 0 0 0 0 0 0 0 */
#define TCNTH   (*(volatile unsigned char *)0x0084) /* Timer Count Register High pp218 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TCNTL   (*(volatile unsigned char *)0x0085) /* Timer Count Register Low pp218 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TSCR   (*(volatile unsigned char *)0x0086) /* Timer System Control Register pp219 bits: TEN TSWAI TSBCK TFFCA Reset: 0 0 0 0 0 0 0 0 */
#define TCTL1   (*(volatile unsigned char *)0x0088) /* Timer Control Register 1 pp220 bits: OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 Reset: 0 0 0 0 0 0 0 0 */
#define TCTL2   (*(volatile unsigned char *)0x0089) /* Timer Control Register 2 pp220 bits: OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 Reset: 0 0 0 0 0 0 0 0 */
#define TCTL3   (*(volatile unsigned char *)0x008A) /* Timer Control Register 3 pp221 bits: EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A Reset: 0 0 0 0 0 0 0 0 */
#define TCTL4   (*(volatile unsigned char *)0x008B) /* Timer Control Register 4 pp221 bits: EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset: 0 0 0 0 0 0 0 0 */
#define TMSK1   (*(volatile unsigned char *)0x008C) /* Timer Mask Register 1 pp222 bits: C7I C6I C5I C4I C3I C2I C1I C0I Reset: 0 0 0 0 0 0 0 0 */
#define TMSK2   (*(volatile unsigned char *)0x008D) /* Timer Mask Register 2 pp223 bits: TOI 0 PUPT RDPT TCRE PR2 PR1 PR0 Reset: 0 0 0 0 0 0 0 0 */
#define TFLG1   (*(volatile unsigned char *)0x008E) /* Timer Interrupt Flag Register 1 pp224 bits: C7F C6F C5F C4F C3F C2F C1F C0F Reset: 0 0 0 0 0 0 0 0 */
#define TFLG2   (*(volatile unsigned char *)0x008F) /* Timer Interrupt Flag Register 2 pp225 bits: TOF 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC0H   (*(volatile unsigned char *)0x0090) /* Timer Input Capture/Output Compare 0 Register High pp226 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC0L   (*(volatile unsigned char *)0x0091) /* Timer Input Capture/Output Compare 0 Register Low pp226 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC1H   (*(volatile unsigned char *)0x0092) /* Timer Input Capture/Output Compare 1 Register High pp226 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC1L   (*(volatile unsigned char *)0x0093) /* Timer Input Capture/Output Compare 1 Register Low pp226 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC2H   (*(volatile unsigned char *)0x0094) /* Timer Input Capture/Output Compare 2 Register High pp227 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC2L   (*(volatile unsigned char *)0x0095) /* Timer Input Capture/Output Compare 2 Register Low pp227 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC3H   (*(volatile unsigned char *)0x0096) /* Timer Input Capture/Output Compare 3 Register High pp228 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC3L   (*(volatile unsigned char *)0x0097) /* Timer Input Capture/Output Compare 3 Register Low pp228 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC4H   (*(volatile unsigned char *)0x0098) /* Timer Input Capture/Output Compare 4 Register High pp228 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC4L   (*(volatile unsigned char *)0x0099) /* Timer Input Capture/Output Compare 4 Register Low pp228 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC5H   (*(volatile unsigned char *)0x009A) /* Timer Input Capture/Output Compare 5 Register High pp228 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC5L   (*(volatile unsigned char *)0x009B) /* Timer Input Capture/Output Compare 5 Register Low pp228 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC6H   (*(volatile unsigned char *)0x009C) /* Timer Input Capture/Output Compare 6 Register High pp229 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC6L   (*(volatile unsigned char *)0x009D) /* Timer Input Capture/Output Compare 6 Register Low pp229 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC7H   (*(volatile unsigned char *)0x009E) /* Timer Input Capture/Output Compare 7 Register High pp229 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC7L   (*(volatile unsigned char *)0x009F) /* Timer Input Capture/Output Compare 7 Register Low pp229 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PACTL   (*(volatile unsigned char *)0x00A0) /* Pulse Accumulator Control Register pp230 bits: 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI Reset: 0 0 0 0 0 0 0 0 */
#define PAFLG   (*(volatile unsigned char *)0x00A1) /* Pulse Accumulator Flag Register pp232 bits: 0 0 0 0 0 0 PAOVF PAIF Reset: 0 0 0 0 0 0 0 0 */
#define PACN3   (*(volatile unsigned char *)0x00A2) /* Pulse Accumulator Count Register 3 pp269 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PACN2   (*(volatile unsigned char *)0x00A3) /* Pulse Accumulator Count Register 2 pp269 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PACN1   (*(volatile unsigned char *)0x00A4) /* Pulse Accumulator Count Register 1 pp270 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PACN0   (*(volatile unsigned char *)0x00A5) /* Pulse Accumulator Count Register 0 pp270 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define MCCTL   (*(volatile unsigned char *)0x00A6) /* 16­Bit Modulus Down­Counter Control Regster pp271 bits: MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0 Reset: 0 0 0 0 0 0 0 0 */
#define MCFLG   (*(volatile unsigned char *)0x00A7) /* 16­Bit Modulus Down­Counter Flag Regster pp273 bits: MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0 Reset: 0 0 0 0 0 0 0 0 */
#define ICPACR   (*(volatile unsigned char *)0x00A8) /* Input Control Pulse Accumulators Control Register pp274 bits: 0 0 0 0 PA3EN PA2EN PA1EN PA0EN Reset: 0 0 0 0 0 0 0 0 */
#define DLYCT   (*(volatile unsigned char *)0x00A9) /* Delay Counter Control Register pp275 bits: 0 0 0 0 0 0 DLY1 DLY0 Reset: 0 0 0 0 0 0 0 0 */
#define ICOVW   (*(volatile unsigned char *)0x00AA) /* Input Control Overwrite Register pp276 bits: NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 Reset: 0 0 0 0 0 0 0 0 */
#define ICSYS   (*(volatile unsigned char *)0x00AB) /* Input Control System Control Register pp276 bits: SH37 SH26 SH15 HS04 TFMOD PACMX BUFEN LATQ Reset: 0 0 0 0 0 0 0 0 */
#define TIMTST   (*(volatile unsigned char *)0x00AD) /* Timer Test Register pp279 bits: 0 0 0 0 0 0 TCBYP PCBYP (1) Reset: 0 0 0 0 0 0 0 0 */
#define PORTT   (*(volatile unsigned char *)0x00AE) /* Timer Port Data Register pp280 bits: PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 Reset: 0 0 0 0 0 0 0 0 */
#define DDRT   (*(volatile unsigned char *)0x00AF) /* Data Direction Register for Timer Port pp281 bits: DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0 Reset: 0 0 0 0 0 0 0 0 */
#define PBCTL   (*(volatile unsigned char *)0x00B0) /* 16­Bit Pulse Accumulator B Control Register pp282 bits: 0 PBEN 0 0 0 0 PBOV 0 Reset: 0 0 0 0 0 0 0 0 */
#define PBFLG   (*(volatile unsigned char *)0x00B1) /* Pulse Accumulator B Flag Register pp283 bits: 0 0 0 0 0 0 PBOV 0 Reset: 0 0 0 0 0 0 0 0 */
#define PA3H   (*(volatile unsigned char *)0x00B2) /* 8­Bit Pulse Accumulator Holding Register 3 pp283 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PA2H   (*(volatile unsigned char *)0x00B3) /* 8­Bit Pulse Accumulator Holding Register 2 pp283 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PA1H   (*(volatile unsigned char *)0x00B4) /* 8­Bit Pulse Accumulator Holding Register 1 pp284 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define PA0H   (*(volatile unsigned char *)0x00B5) /* 8­Bit Pulse Accumulator Holding Register 0 pp284 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define MCCNT_H   (*(volatile unsigned char *)0x00B6) /* Modulus Down­Counter Count Register pp285 bits: Bit15 14 13 12 11 10 9 8 Reset: 1 1 1 1 1 1 1 1 */
#define MCCNT_L   (*(volatile unsigned char *)0x00B7) /* Modulus Down­Counter Count Register pp285 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
#define TC0H_H   (*(volatile unsigned char *)0x00B8) /* Timer Input Capture Holding Register 0 pp286 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 1 0 0 0 0 0 */
#define TC0H_L   (*(volatile unsigned char *)0x00B9) /* Timer Input Capture Holding Register 0 pp286 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC1H_H   (*(volatile unsigned char *)0x00BA) /* Timer Input Capture Holding Register 1 pp286 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC1H_L   (*(volatile unsigned char *)0x00BB) /* Timer Input Capture Holding Register 1 pp286 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC2H_H   (*(volatile unsigned char *)0x00BC) /* Timer Input Capture Holding Register 2 pp287 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC2H_L   (*(volatile unsigned char *)0x00BD) /* Timer Input Capture Holding Register 2 pp287 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define TC3H_H   (*(volatile unsigned char *)0x00BE) /* Timer Input Capture Holding Register 3 pp287 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
#define TC3H_L   (*(volatile unsigned char *)0x00BF) /* Timer Input Capture Holding Register 3 pp287 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
#define SC0BDH   (*(volatile unsigned char *)0x00C0) /* SCI 0 Baud Rate Control Register High pp294 bits: BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 Reset: 0 0 0 0 0 0 0 0 */
#define SC0BDL   (*(volatile unsigned char *)0x00C1) /* SCI 0 Baud Rate Control Register Low pp294 bits: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Reset: 0 0 0 0 0 1 0 0 */
#define SC0CR1   (*(volatile unsigned char *)0x00C2) /* SCI Control Register 1 pp295 bits: LOOPS WOMS RSRC M WAKE ILT PE PT Reset: 0 0 0 0 0 0 0 0 */
#define SC0CR2   (*(volatile unsigned char *)0x00C3) /* SCI Control Register 2 pp298 bits: TIE TCIE RIE ILIE TE RE RWU SBK Reset: 0 0 0 0 0 0 0 0 */
#define SC0SR1   (*(volatile unsigned char *)0x00C4) /* SCI Status Register 1 pp299 bits: TDRE TC RDRF IDLE OR NF FE PF Reset: 1 1 0 0 0 0 0 0 */
#define SC0SR2   (*(volatile unsigned char *)0x00C5) /* SCI Status Register 2 pp301 bits: 0 0 0 0 0 0 0 RAF Reset: 0 0 0 0 0 0 0 0 */
#define SC0DRH   (*(volatile unsigned char *)0x00C6) /* SCI Data Register High pp302 bits: R8 T8 0 0 0 0 0 0 Reset: U U 0 0 0 0 0 0 */
#define SC0DRL   (*(volatile unsigned char *)0x00C7) /* SCI Data Register Low pp302 bits: R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Reset: Unaffected by reset */
#define SP0CR1   (*(volatile unsigned char *)0x00D0) /* SPI Control Register 1 pp308 bits: SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF Reset: 0 0 0 0 0 0 0 0 */
#define SP0CR2   (*(volatile unsigned char *)0x00D1) /* SPI Control Register 2 pp310 bits: 0 0 0 0 PUPS RDS 0 SPC0 Reset: 0 0 0 0 1 0 0 0 */
#define SP0BR   (*(volatile unsigned char *)0x00D2) /* SPI Baud Rate Register pp311 bits: 0 0 0 0 0 SPR2 SPR1 SPR0 Reset: 0 0 0 0 0 0 0 0 */
#define SP0SR   (*(volatile unsigned char *)0x00D3) /* SPI Status Register pp312 bits: SPIF WCOL 0 MODF 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define SP0DR   (*(volatile unsigned char *)0x00D5) /* SPI Data Register pp313 bits: Bit7 6 5 4 3 2 1 0 Reset: Unaffected by reset */
#define PORTS   (*(volatile unsigned char *)0x00D6) /* Port S Data Register pp314 bits: PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 Reset: After reset all bits configured as general­purpose inputs */
#define DDRS   (*(volatile unsigned char *)0x00D7) /* Port S Data Direction Register pp315 bits: DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0 Reset: After reset all bits configured as general­purpose inputs */
#define PURDS   (*(volatile unsigned char *)0x00DB) /* Port S Pullup/Reduced Drive Register pp316 bits: 0 RDPS2 RDPS1 RDPS0 0 PUPS2 PUPS1 PUPS0 Reset: 0 0 0 0 0 0 0 0 */
#define SLOW   (*(volatile unsigned char *)0x00E0) /* Slow Mode Divider Register pp179 bits: 0 0 0 0 0 SLDV2 SLDV1 SLDV0 Reset: 0 0 0 0 0 0 0 0 */
#define EEMCR   (*(volatile unsigned char *)0x00F0) /* EEPROM Configuration Register pp146 bits: 1 1 1 1 1 EESWAI PROTLCK EERC Reset: 1 1 1 1 1 1 0 0 */
#define EEPROT   (*(volatile unsigned char *)0x00F1) /* EEPROM Block Protect Register pp147 bits: 1 1 1 BRPROT4 BRPROT3 BRPROT2 BRPROT1 BRPROT0 Reset: 1 1 1 1 1 1 1 1 */
#define EETST   (*(volatile unsigned char *)0x00F2) /* EEPROM Test Register pp148 bits: EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 Reset: 0 0 0 0 0 0 0 0 */
#define EEPROG   (*(volatile unsigned char *)0x00F3) /* EEPROM Control Register pp149 bits: BULKP 0 0 BYTE ROW ERASE EELAT EEPGM Reset: 1 0 0 0 0 0 0 0 */
#define FEELCK   (*(volatile unsigned char *)0x00F4) /* FLASH EEPROM Lock Control Register pp155 bits: 0 0 0 0 0 0 0 LOCK Reset: 0 0 0 0 0 0 0 0 */
#define FEEMCR   (*(volatile unsigned char *)0x00F5) /* FLASH EEPROM Configuration Register pp156 bits: 0 0 0 0 0 0 0 BOOTP Reset: 0 0 0 0 0 0 0 1 */
#define FEETST   (*(volatile unsigned char *)0x00F6) /* FLASH EEPROM Test Register pp156 bits: FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR Reset: 0 0 0 0 0 0 0 0 */
#define FEECTL   (*(volatile unsigned char *)0x00F7) /* FLASH EEPROM Control Register pp158 bits: 0 0 0 FEESWAI SVFP ERAS LAT ENPE Reset: 0 0 0 0 0 0 0 0 */
#define BCR1   (*(volatile unsigned char *)0x00F8) /* BDLC Control Register 1 pp351 bits: IMSG CLKS R1 R0 0 0 IE WCM Write: R R Reset: 1 1 1 0 0 0 0 0 */
#define BSVR   (*(volatile unsigned char *)0x00F9) /* BDLC State Vector Register pp360 bits: 0 0 I3 I2 I1 I0 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define BCR2   (*(volatile unsigned char *)0x00FA) /* BDLC Control Register 2 pp353 bits: ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 Reset: 1 1 0 0 0 0 0 0 */
#define BDR   (*(volatile unsigned char *)0x00FB) /* BDLC Data Register pp363 bits: BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 Reset: Indeterminate after reset */
#define BARD   (*(volatile unsigned char *)0x00FC) /* BDLC Analog Roundtrip Delay Register pp364 bits: ATE RXPOL 0 0 BO3 BO2 BO1 BO0 Reset: 1 1 0 0 0 1 1 1 */
#define DLCSCR   (*(volatile unsigned char *)0x00FD) /* Port DLC Control Register pp366 bits: 0 0 0 0 0 BDLCEN PUPDLC RDPDLC Reset: 0 0 0 0 0 0 0 0 */
#define PORTDLC   (*(volatile unsigned char *)0x00FE) /* Port DLC Data Register pp367 bits: 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: 0 U U U U U U U */
#define DDRDLC   (*(volatile unsigned char *)0x00FF) /* Port DLC Data Direction Register pp368 bits: 0 DDDLC6 DDDLC5 DDDLC4 DDDLC3 DDDLC2 DDDLC1 DDDLC0 Reset: 0 0 0 0 0 0 0 0 */
#define CMCR0   (*(volatile unsigned char *)0x0100) /* msCAN12 Module Control Register 0 pp397 bits: 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES Reset: 0 0 1 0 0 0 0 1 */
#define CMCR1   (*(volatile unsigned char *)0x0101) /* msCAN12 Module Control Register 1 pp399 bits: 0 0 0 0 0 LOOPB WUPM CLKSRC Reset: 0 0 0 0 0 0 0 0 */
#define CBTR0   (*(volatile unsigned char *)0x0102) /* msCAN12 Bus Timing Register 0 pp400 bits: SJW1 SJW0 BRP5 BRP4 BPR3 BPR2 BPR1 BPR0 Reset: 0 0 0 0 0 0 0 0 */
#define CBTR1   (*(volatile unsigned char *)0x0103) /* msCAN12 Bus Timing Register 1 pp401 bits: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Reset: 0 0 0 0 0 0 0 0 */
#define CRFLG   (*(volatile unsigned char *)0x0104) /* msCAN12 Receiver Flag Register pp403 bits: WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF Reset: 0 0 0 0 0 0 0 0 */
#define CRIER   (*(volatile unsigned char *)0x0105) /* msCAN12 Receiver Interrupt Enable Register pp405 bits: WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE Reset: 0 0 0 0 0 0 0 0 */
#define CTFLG   (*(volatile unsigned char *)0x0106) /* msCAN12 Transmitter Flag Register pp407 bits: 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0 Reset: 0 0 0 0 0 1 1 1 */
#define CTCR   (*(volatile unsigned char *)0x0107) /* msCAN12 Transmitter Control Register pp408 bits: 0 ABTRQ2 ABTRQ1 ABTRQ0 0 TXEIE2 TXEIE1 TXEIE0 Reset: 0 0 0 0 0 0 0 0 */
#define CIDAC   (*(volatile unsigned char *)0x0108) /* msCAN12 Identifier Acceptance Control Register pp409 bits: 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 Reset: 0 0 0 0 0 0 0 0 */
#define CRXERR   (*(volatile unsigned char *)0x010E) /* msCAN12 Receive Error Counter pp410 bits: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Reset: 0 0 0 0 0 0 0 0 */
#define CTXERR   (*(volatile unsigned char *)0x010F) /* msCAN12 Transmit Error Counter pp411 bits: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Reset: 0 0 0 0 0 0 0 0 */
#define CIDAR0   (*(volatile unsigned char *)0x0110) /* msCAN12 Identifier Acceptance Register 0 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDAR1   (*(volatile unsigned char *)0x0111) /* msCAN12 Identifier Acceptance Register 1 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDAR2   (*(volatile unsigned char *)0x0112) /* msCAN12 Identifier Acceptance Register 2 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDAR3   (*(volatile unsigned char *)0x0113) /* msCAN12 Identifier Acceptance Register 3 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDMR0   (*(volatile unsigned char *)0x0114) /* msCAN12 Identifier Mask Register 0 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define CIDMR1   (*(volatile unsigned char *)0x0115) /* msCAN12 Identifier Mask Register 1 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define CIDMR2   (*(volatile unsigned char *)0x0116) /* msCAN12 Identifier Mask Register 2 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define CIDMR3   (*(volatile unsigned char *)0x0117) /* msCAN12 Identifier Mask Register 3 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define CIDAR4   (*(volatile unsigned char *)0x0118) /* msCAN12 Identifier Acceptance Register 4 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDAR5   (*(volatile unsigned char *)0x0119) /* msCAN12 Identifier Acceptance Register 5 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDAR6   (*(volatile unsigned char *)0x011A) /* msCAN12 Identifier Acceptance Register 6 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDAR7   (*(volatile unsigned char *)0x011B) /* msCAN12 Identifier Acceptance Register 7 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
#define CIDMR4   (*(volatile unsigned char *)0x011C) /* msCAN12 Identifier Mask Register 4 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define CIDMR5   (*(volatile unsigned char *)0x011D) /* msCAN12 Identifier Mask Register 5 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define CIDMR6   (*(volatile unsigned char *)0x011E) /* msCAN12 Identifier Mask Register 6 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define CIDMR7   (*(volatile unsigned char *)0x011F) /* msCAN12 Identifier Mask Register 7 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
#define PCTLCAN   (*(volatile unsigned char *)0x013D) /* msCAN12 Port CAN Control Register pp416 bits: 0 0 0 0 0 0 PUECAN RDPCAN Reset: 0 0 0 0 0 0 0 0 */
#define PORTCAN   (*(volatile unsigned char *)0x013E) /* msCAN12 Port CAN Data Register pp417 bits: PCAN7 PCAN6 PCAN5 PCAN4 PCAN2 PCAN2 TxCAN RxCAN Reset: Unaffected by reset */
#define DDRCAN   (*(volatile unsigned char *)0x013F) /* msCAN12 Port CAN Data Direction Register pp418 bits: DDRCAN7 DDRCAN6 DDRCAN5 DDRCAN4 DDRCAN3 DDRCAN2 0 0 Reset: 0 0 0 0 0 0 0 0 */
#define RxFG   (*(volatile unsigned char *)0x0140) /* RECEIVE BUFFER (3) --- SEE 16.4.2 Receive Structures */


Define Documentation

#define ADRx0H   (*(volatile unsigned char *)0x0070) /* ATD Result Register 0 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 153 of file asm-m68hc12b/ports.h.

#define ADRx0L   (*(volatile unsigned char *)0x0071) /* ATD Result Register 0 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 155 of file asm-m68hc12b/ports.h.

#define ADRx1H   (*(volatile unsigned char *)0x0072) /* ATD Result Register 1 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 157 of file asm-m68hc12b/ports.h.

#define ADRx1L   (*(volatile unsigned char *)0x0073) /* ATD Result Register 1 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 159 of file asm-m68hc12b/ports.h.

#define ADRx2H   (*(volatile unsigned char *)0x0074) /* ATD Result Register 2 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 161 of file asm-m68hc12b/ports.h.

#define ADRx2L   (*(volatile unsigned char *)0x0075) /* ATD Result Register 2 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 163 of file asm-m68hc12b/ports.h.

#define ADRx3H   (*(volatile unsigned char *)0x0076) /* ATD Result Register 3 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 165 of file asm-m68hc12b/ports.h.

#define ADRx3L   (*(volatile unsigned char *)0x0077) /* ATD Result Register 3 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 167 of file asm-m68hc12b/ports.h.

#define ADRx4H   (*(volatile unsigned char *)0x0078) /* ATD Result Register 4 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 169 of file asm-m68hc12b/ports.h.

#define ADRx4L   (*(volatile unsigned char *)0x0079) /* ATD Result Register 4 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 171 of file asm-m68hc12b/ports.h.

#define ADRx5H   (*(volatile unsigned char *)0x007A) /* ATD Result Register 5 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 173 of file asm-m68hc12b/ports.h.

#define ADRx5L   (*(volatile unsigned char *)0x007B) /* ATD Result Register 5 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 175 of file asm-m68hc12b/ports.h.

#define ADRx6H   (*(volatile unsigned char *)0x007C) /* ATD Result Register 6 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 177 of file asm-m68hc12b/ports.h.

#define ADRx6L   (*(volatile unsigned char *)0x007D) /* ATD Result Register 6 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 179 of file asm-m68hc12b/ports.h.

#define ADRx7H   (*(volatile unsigned char *)0x007E) /* ATD Result Register 7 pp432 bits: Bit15 14 13 12 11 10 9 8 Reset: Undefined */
 

Definition at line 181 of file asm-m68hc12b/ports.h.

#define ADRx7L   (*(volatile unsigned char *)0x007F) /* ATD Result Register 7 pp432 bits: Bit7 6 5 4 3 2 1 0 Reset: Undefined */
 

Definition at line 183 of file asm-m68hc12b/ports.h.

#define ATDCTL0   (*(volatile unsigned char *)0x0060) /* ATD Control Register 0 pp422 bits: 0 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 129 of file asm-m68hc12b/ports.h.

#define ATDCTL1   (*(volatile unsigned char *)0x0061) /* ATD Control Register 1 pp422 bits: 0 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 131 of file asm-m68hc12b/ports.h.

#define ATDCTL2   (*(volatile unsigned char *)0x0062) /* ATD Control Register 2 pp423 bits: ADPU AFFC AWAI 0 0 0 ASCIE ASCIF Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 133 of file asm-m68hc12b/ports.h.

#define ATDCTL3   (*(volatile unsigned char *)0x0063) /* ATD Control Register 3 pp424 bits: 0 0 0 0 0 0 FRZ1 FRZ0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 135 of file asm-m68hc12b/ports.h.

#define ATDCTL4   (*(volatile unsigned char *)0x0064) /* ATD Control Register 4 pp425 bits: S10BM SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Reset: 0 0 0 0 0 0 0 1 */
 

Definition at line 137 of file asm-m68hc12b/ports.h.

#define ATDCTL5   (*(volatile unsigned char *)0x0065) /* ATD Control Register 5 pp427 bits: S8CM SCAN MULT CD CC CB CA Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 139 of file asm-m68hc12b/ports.h.

#define ATDSTAT_H   (*(volatile unsigned char *)0x0066) /* ATD Status Register pp429 bits: SCF 0 0 0 0 CC2 CC1 CC0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 141 of file asm-m68hc12b/ports.h.

#define ATDSTAT_L   (*(volatile unsigned char *)0x0067) /* ATD Status Register pp429 bits: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 143 of file asm-m68hc12b/ports.h.

#define ATDTSTH   (*(volatile unsigned char *)0x0068) /* ATD Test Register High pp430 bits: SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 145 of file asm-m68hc12b/ports.h.

#define ATDTSTL   (*(volatile unsigned char *)0x0069) /* ATD Test Register Low pp430 bits: SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 147 of file asm-m68hc12b/ports.h.

#define BARD   (*(volatile unsigned char *)0x00FC) /* BDLC Analog Roundtrip Delay Register pp364 bits: ATE RXPOL 0 0 BO3 BO2 BO1 BO0 Reset: 1 1 0 0 0 1 1 1 */
 

Definition at line 378 of file asm-m68hc12b/ports.h.

#define BCR1   (*(volatile unsigned char *)0x00F8) /* BDLC Control Register 1 pp351 bits: IMSG CLKS R1 R0 0 0 IE WCM Write: R R Reset: 1 1 1 0 0 0 0 0 */
 

Definition at line 370 of file asm-m68hc12b/ports.h.

#define BCR2   (*(volatile unsigned char *)0x00FA) /* BDLC Control Register 2 pp353 bits: ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 Reset: 1 1 0 0 0 0 0 0 */
 

Definition at line 374 of file asm-m68hc12b/ports.h.

#define BDR   (*(volatile unsigned char *)0x00FB) /* BDLC Data Register pp363 bits: BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 Reset: Indeterminate after reset */
 

Definition at line 376 of file asm-m68hc12b/ports.h.

#define BRKAH   (*(volatile unsigned char *)0x0022) /* Breakpoint Address Register High pp461 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 69 of file asm-m68hc12b/ports.h.

#define BRKAL   (*(volatile unsigned char *)0x0023) /* Breakpoint Address Register Low pp462 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 71 of file asm-m68hc12b/ports.h.

#define BRKCT0   (*(volatile unsigned char *)0x0020) /* Breakpoint Control Register 0 pp458 bits: BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 65 of file asm-m68hc12b/ports.h.

#define BRKCT1   (*(volatile unsigned char *)0x0021) /* Breakpoint Control Register 1 pp459 bits: 0 BKDBE BKMBH BKMBL BK1RWE BK1RW BK0RWE BK0RW Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 67 of file asm-m68hc12b/ports.h.

#define BRKDH   (*(volatile unsigned char *)0x0024) /* Breakpoint Data Register High pp462 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 73 of file asm-m68hc12b/ports.h.

#define BRKDL   (*(volatile unsigned char *)0x0025) /* Breakpoint Data Register Low pp463 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 75 of file asm-m68hc12b/ports.h.

#define BSVR   (*(volatile unsigned char *)0x00F9) /* BDLC State Vector Register pp360 bits: 0 0 I3 I2 I1 I0 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 372 of file asm-m68hc12b/ports.h.

#define CBTR0   (*(volatile unsigned char *)0x0102) /* msCAN12 Bus Timing Register 0 pp400 bits: SJW1 SJW0 BRP5 BRP4 BPR3 BPR2 BPR1 BPR0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 390 of file asm-m68hc12b/ports.h.

#define CBTR1   (*(volatile unsigned char *)0x0103) /* msCAN12 Bus Timing Register 1 pp401 bits: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 392 of file asm-m68hc12b/ports.h.

#define CFORC   (*(volatile unsigned char *)0x0081) /* Timer Compare Force Register pp216 bits: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 187 of file asm-m68hc12b/ports.h.

#define CIDAC   (*(volatile unsigned char *)0x0108) /* msCAN12 Identifier Acceptance Control Register pp409 bits: 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 402 of file asm-m68hc12b/ports.h.

#define CIDAR0   (*(volatile unsigned char *)0x0110) /* msCAN12 Identifier Acceptance Register 0 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 410 of file asm-m68hc12b/ports.h.

#define CIDAR1   (*(volatile unsigned char *)0x0111) /* msCAN12 Identifier Acceptance Register 1 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 412 of file asm-m68hc12b/ports.h.

#define CIDAR2   (*(volatile unsigned char *)0x0112) /* msCAN12 Identifier Acceptance Register 2 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 414 of file asm-m68hc12b/ports.h.

#define CIDAR3   (*(volatile unsigned char *)0x0113) /* msCAN12 Identifier Acceptance Register 3 pp412 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 416 of file asm-m68hc12b/ports.h.

#define CIDAR4   (*(volatile unsigned char *)0x0118) /* msCAN12 Identifier Acceptance Register 4 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 426 of file asm-m68hc12b/ports.h.

#define CIDAR5   (*(volatile unsigned char *)0x0119) /* msCAN12 Identifier Acceptance Register 5 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 428 of file asm-m68hc12b/ports.h.

#define CIDAR6   (*(volatile unsigned char *)0x011A) /* msCAN12 Identifier Acceptance Register 6 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 430 of file asm-m68hc12b/ports.h.

#define CIDAR7   (*(volatile unsigned char *)0x011B) /* msCAN12 Identifier Acceptance Register 7 pp413 bits: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Reset: Unaffected by reset */
 

Definition at line 432 of file asm-m68hc12b/ports.h.

#define CIDMR0   (*(volatile unsigned char *)0x0114) /* msCAN12 Identifier Mask Register 0 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 418 of file asm-m68hc12b/ports.h.

#define CIDMR1   (*(volatile unsigned char *)0x0115) /* msCAN12 Identifier Mask Register 1 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 420 of file asm-m68hc12b/ports.h.

#define CIDMR2   (*(volatile unsigned char *)0x0116) /* msCAN12 Identifier Mask Register 2 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 422 of file asm-m68hc12b/ports.h.

#define CIDMR3   (*(volatile unsigned char *)0x0117) /* msCAN12 Identifier Mask Register 3 pp414 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 424 of file asm-m68hc12b/ports.h.

#define CIDMR4   (*(volatile unsigned char *)0x011C) /* msCAN12 Identifier Mask Register 4 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 434 of file asm-m68hc12b/ports.h.

#define CIDMR5   (*(volatile unsigned char *)0x011D) /* msCAN12 Identifier Mask Register 5 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 436 of file asm-m68hc12b/ports.h.

#define CIDMR6   (*(volatile unsigned char *)0x011E) /* msCAN12 Identifier Mask Register 6 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 438 of file asm-m68hc12b/ports.h.

#define CIDMR7   (*(volatile unsigned char *)0x011F) /* msCAN12 Identifier Mask Register 7 pp415 bits: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Reset: Unaffected by reset */
 

Definition at line 440 of file asm-m68hc12b/ports.h.

#define CMCR0   (*(volatile unsigned char *)0x0100) /* msCAN12 Module Control Register 0 pp397 bits: 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES Reset: 0 0 1 0 0 0 0 1 */
 

Definition at line 386 of file asm-m68hc12b/ports.h.

#define CMCR1   (*(volatile unsigned char *)0x0101) /* msCAN12 Module Control Register 1 pp399 bits: 0 0 0 0 0 LOOPB WUPM CLKSRC Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 388 of file asm-m68hc12b/ports.h.

#define COPCTL   (*(volatile unsigned char *)0x0016) /* COP Control Register pp182 bits: CME FCME FCM FCOP DISR CR2 CR1 CR0 Reset: 0 0 0 0 0 0 0 1 */
 

Definition at line 55 of file asm-m68hc12b/ports.h.

#define COPRST   (*(volatile unsigned char *)0x0017) /* Arm/Reset COP Timer Register pp184 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 57 of file asm-m68hc12b/ports.h.

#define CRFLG   (*(volatile unsigned char *)0x0104) /* msCAN12 Receiver Flag Register pp403 bits: WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 394 of file asm-m68hc12b/ports.h.

#define CRIER   (*(volatile unsigned char *)0x0105) /* msCAN12 Receiver Interrupt Enable Register pp405 bits: WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 396 of file asm-m68hc12b/ports.h.

#define CRXERR   (*(volatile unsigned char *)0x010E) /* msCAN12 Receive Error Counter pp410 bits: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 406 of file asm-m68hc12b/ports.h.

#define CTCR   (*(volatile unsigned char *)0x0107) /* msCAN12 Transmitter Control Register pp408 bits: 0 ABTRQ2 ABTRQ1 ABTRQ0 0 TXEIE2 TXEIE1 TXEIE0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 400 of file asm-m68hc12b/ports.h.

#define CTFLG   (*(volatile unsigned char *)0x0106) /* msCAN12 Transmitter Flag Register pp407 bits: 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0 Reset: 0 0 0 0 0 1 1 1 */
 

Definition at line 398 of file asm-m68hc12b/ports.h.

#define CTXERR   (*(volatile unsigned char *)0x010F) /* msCAN12 Transmit Error Counter pp411 bits: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 408 of file asm-m68hc12b/ports.h.

#define DDRA   (*(volatile unsigned char *)0x0002) /* Data Direction Register A pp132 bits: DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 23 of file asm-m68hc12b/ports.h.

#define DDRB   (*(volatile unsigned char *)0x0003) /* Data Direction Register B pp134 bits: DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 25 of file asm-m68hc12b/ports.h.

#define DDRCAN   (*(volatile unsigned char *)0x013F) /* msCAN12 Port CAN Data Direction Register pp418 bits: DDRCAN7 DDRCAN6 DDRCAN5 DDRCAN4 DDRCAN3 DDRCAN2 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 448 of file asm-m68hc12b/ports.h.

#define DDRDLC   (*(volatile unsigned char *)0x00FF) /* Port DLC Data Direction Register pp368 bits: 0 DDDLC6 DDDLC5 DDDLC4 DDDLC3 DDDLC2 DDDLC1 DDDLC0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 384 of file asm-m68hc12b/ports.h.

#define DDRE   (*(volatile unsigned char *)0x0009) /* Data Direction Register E pp136 bits: DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 0 0 Reset: 0 0 0 0 1 0 0 0 */
 

Definition at line 31 of file asm-m68hc12b/ports.h.

#define DDRP   (*(volatile unsigned char *)0x0057) /* Port P Data Direction Register pp208 bits: DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 125 of file asm-m68hc12b/ports.h.

#define DDRS   (*(volatile unsigned char *)0x00D7) /* Port S Data Direction Register pp315 bits: DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0 Reset: After reset all bits configured as general­purpose inputs */
 

Definition at line 342 of file asm-m68hc12b/ports.h.

#define DDRT   (*(volatile unsigned char *)0x00AF) /* Data Direction Register for Timer Port pp281 bits: DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 277 of file asm-m68hc12b/ports.h.

#define DLCSCR   (*(volatile unsigned char *)0x00FD) /* Port DLC Control Register pp366 bits: 0 0 0 0 0 BDLCEN PUPDLC RDPDLC Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 380 of file asm-m68hc12b/ports.h.

#define DLYCT   (*(volatile unsigned char *)0x00A9) /* Delay Counter Control Register pp275 bits: 0 0 0 0 0 0 DLY1 DLY0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 266 of file asm-m68hc12b/ports.h.

#define EEMCR   (*(volatile unsigned char *)0x00F0) /* EEPROM Configuration Register pp146 bits: 1 1 1 1 1 EESWAI PROTLCK EERC Reset: 1 1 1 1 1 1 0 0 */
 

Definition at line 354 of file asm-m68hc12b/ports.h.

#define EEPROG   (*(volatile unsigned char *)0x00F3) /* EEPROM Control Register pp149 bits: BULKP 0 0 BYTE ROW ERASE EELAT EEPGM Reset: 1 0 0 0 0 0 0 0 */
 

Definition at line 360 of file asm-m68hc12b/ports.h.

#define EEPROT   (*(volatile unsigned char *)0x00F1) /* EEPROM Block Protect Register pp147 bits: 1 1 1 BRPROT4 BRPROT3 BRPROT2 BRPROT1 BRPROT0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 356 of file asm-m68hc12b/ports.h.

#define EETST   (*(volatile unsigned char *)0x00F2) /* EEPROM Test Register pp148 bits: EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 358 of file asm-m68hc12b/ports.h.

#define FEECTL   (*(volatile unsigned char *)0x00F7) /* FLASH EEPROM Control Register pp158 bits: 0 0 0 FEESWAI SVFP ERAS LAT ENPE Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 368 of file asm-m68hc12b/ports.h.

#define FEELCK   (*(volatile unsigned char *)0x00F4) /* FLASH EEPROM Lock Control Register pp155 bits: 0 0 0 0 0 0 0 LOCK Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 362 of file asm-m68hc12b/ports.h.

#define FEEMCR   (*(volatile unsigned char *)0x00F5) /* FLASH EEPROM Configuration Register pp156 bits: 0 0 0 0 0 0 0 BOOTP Reset: 0 0 0 0 0 0 0 1 */
 

Definition at line 364 of file asm-m68hc12b/ports.h.

#define FEETST   (*(volatile unsigned char *)0x00F6) /* FLASH EEPROM Test Register pp156 bits: FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 366 of file asm-m68hc12b/ports.h.

#define HPRIO   (*(volatile unsigned char *)0x001F) /* Highest Priority I Interrupt Register pp109 bits: 1 1 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 Reset: 1 1 1 1 0 0 1 0 */
 

Definition at line 63 of file asm-m68hc12b/ports.h.

#define ICOVW   (*(volatile unsigned char *)0x00AA) /* Input Control Overwrite Register pp276 bits: NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 268 of file asm-m68hc12b/ports.h.

#define ICPACR   (*(volatile unsigned char *)0x00A8) /* Input Control Pulse Accumulators Control Register pp274 bits: 0 0 0 0 PA3EN PA2EN PA1EN PA0EN Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 264 of file asm-m68hc12b/ports.h.

#define ICSYS   (*(volatile unsigned char *)0x00AB) /* Input Control System Control Register pp276 bits: SH37 SH26 SH15 HS04 TFMOD PACMX BUFEN LATQ Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 270 of file asm-m68hc12b/ports.h.

#define INITEE   (*(volatile unsigned char *)0x0012) /* EEPROM Initialization Register pp125 bits: EE15 EE14 EE13 EE12 0 0 0 EEON Reset: 0 0 0 1 0 0 0 1 */
 

Definition at line 47 of file asm-m68hc12b/ports.h.

#define INITRG   (*(volatile unsigned char *)0x0011) /* Register Initialization Register pp123 bits: REG15 REG14 REG13 REG12 REG11 0 0 MMSWAI Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 45 of file asm-m68hc12b/ports.h.

#define INITRM   (*(volatile unsigned char *)0x0010) /* RAM Initialization Register pp124 bits: RAM15 RAM14 RAM13 RAM12 RAM11 0 0 0 Reset: 0 0 0 0 1 0 0 0 */
 

Definition at line 43 of file asm-m68hc12b/ports.h.

#define INTCR   (*(volatile unsigned char *)0x001E) /* Interrupt Control Register pp108 bits: IRQE IRQEN DLY 0 0 0 0 0 Reset: 0 1 1 0 0 0 0 0 */
 

Definition at line 61 of file asm-m68hc12b/ports.h.

#define MCCNT_H   (*(volatile unsigned char *)0x00B6) /* Modulus Down­Counter Count Register pp285 bits: Bit15 14 13 12 11 10 9 8 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 291 of file asm-m68hc12b/ports.h.

#define MCCNT_L   (*(volatile unsigned char *)0x00B7) /* Modulus Down­Counter Count Register pp285 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 293 of file asm-m68hc12b/ports.h.

#define MCCTL   (*(volatile unsigned char *)0x00A6) /* 16­Bit Modulus Down­Counter Control Regster pp271 bits: MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 260 of file asm-m68hc12b/ports.h.

#define MCFLG   (*(volatile unsigned char *)0x00A7) /* 16­Bit Modulus Down­Counter Flag Regster pp273 bits: MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 262 of file asm-m68hc12b/ports.h.

#define MISC   (*(volatile unsigned char *)0x0013) /* Miscellaneous Mapping Control Register pp126 bits: 0 NDRF RFSTR1 RFSTR0 EXSTR1 EXSTR0 MAPROM ROMON Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 49 of file asm-m68hc12b/ports.h.

#define MODE   (*(volatile unsigned char *)0x000B) /* Mode Register pp121 bits: SMODN MODB MODA ESTR IVIS EBSWAI 0 EME Reset: 0 0 0 1 1 0 0 1 */
 

Definition at line 35 of file asm-m68hc12b/ports.h.

#define OC7D   (*(volatile unsigned char *)0x0083) /* Timer Output Compare 7 Data Register pp217 bits: OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 191 of file asm-m68hc12b/ports.h.

#define OC7M   (*(volatile unsigned char *)0x0082) /* Timer Output Compare 7 Mask Register pp217 bits: OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 189 of file asm-m68hc12b/ports.h.

#define PA0H   (*(volatile unsigned char *)0x00B5) /* 8­Bit Pulse Accumulator Holding Register 0 pp284 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 289 of file asm-m68hc12b/ports.h.

#define PA1H   (*(volatile unsigned char *)0x00B4) /* 8­Bit Pulse Accumulator Holding Register 1 pp284 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 287 of file asm-m68hc12b/ports.h.

#define PA2H   (*(volatile unsigned char *)0x00B3) /* 8­Bit Pulse Accumulator Holding Register 2 pp283 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 285 of file asm-m68hc12b/ports.h.

#define PA3H   (*(volatile unsigned char *)0x00B2) /* 8­Bit Pulse Accumulator Holding Register 3 pp283 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 283 of file asm-m68hc12b/ports.h.

#define PACN0   (*(volatile unsigned char *)0x00A5) /* Pulse Accumulator Count Register 0 pp270 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 258 of file asm-m68hc12b/ports.h.

#define PACN1   (*(volatile unsigned char *)0x00A4) /* Pulse Accumulator Count Register 1 pp270 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 256 of file asm-m68hc12b/ports.h.

#define PACN2   (*(volatile unsigned char *)0x00A3) /* Pulse Accumulator Count Register 2 pp269 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 254 of file asm-m68hc12b/ports.h.

#define PACN3   (*(volatile unsigned char *)0x00A2) /* Pulse Accumulator Count Register 3 pp269 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 252 of file asm-m68hc12b/ports.h.

#define PACTL   (*(volatile unsigned char *)0x00A0) /* Pulse Accumulator Control Register pp230 bits: 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 248 of file asm-m68hc12b/ports.h.

#define PAFLG   (*(volatile unsigned char *)0x00A1) /* Pulse Accumulator Flag Register pp232 bits: 0 0 0 0 0 0 PAOVF PAIF Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 250 of file asm-m68hc12b/ports.h.

#define PBCTL   (*(volatile unsigned char *)0x00B0) /* 16­Bit Pulse Accumulator B Control Register pp282 bits: 0 PBEN 0 0 0 0 PBOV 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 279 of file asm-m68hc12b/ports.h.

#define PBFLG   (*(volatile unsigned char *)0x00B1) /* Pulse Accumulator B Flag Register pp283 bits: 0 0 0 0 0 0 PBOV 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 281 of file asm-m68hc12b/ports.h.

#define PCTLCAN   (*(volatile unsigned char *)0x013D) /* msCAN12 Port CAN Control Register pp416 bits: 0 0 0 0 0 0 PUECAN RDPCAN Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 444 of file asm-m68hc12b/ports.h.

#define PEAR   (*(volatile unsigned char *)0x000A) /* Port E Assignment Register pp137 bits: NDBE CGMTE PIPOE NECLK LSTRE RDWE 0 0 Reset: 1 0 0 1 0 0 0 0 */
 

Definition at line 33 of file asm-m68hc12b/ports.h.

#define PORTA   (*(volatile unsigned char *)0x0000) /* Port A Data Register pp131 bits: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Reset: U U U U U U U U */
 

Definition at line 19 of file asm-m68hc12b/ports.h.

#define PORTAD   (*(volatile unsigned char *)0x006F) /* Port AD Data Input Register pp431 bits: PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 Reset: After reset, reflect the state of the input pins */
 

Definition at line 151 of file asm-m68hc12b/ports.h.

#define PORTB   (*(volatile unsigned char *)0x0001) /* Port B Data Register pp133 bits: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Reset: U U U U U U U U */
 

Definition at line 21 of file asm-m68hc12b/ports.h.

#define PORTCAN   (*(volatile unsigned char *)0x013E) /* msCAN12 Port CAN Data Register pp417 bits: PCAN7 PCAN6 PCAN5 PCAN4 PCAN2 PCAN2 TxCAN RxCAN Reset: Unaffected by reset */
 

Definition at line 446 of file asm-m68hc12b/ports.h.

#define PORTDLC   (*(volatile unsigned char *)0x00FE) /* Port DLC Data Register pp367 bits: 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: 0 U U U U U U U */
 

Definition at line 382 of file asm-m68hc12b/ports.h.

#define PORTE   (*(volatile unsigned char *)0x0008) /* Port E Data Register pp135 bits: PE7 PE6 PE5 PD4 PD3 PD2 PD1 PD0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 29 of file asm-m68hc12b/ports.h.

#define PORTP   (*(volatile unsigned char *)0x0056) /* Port P Data Register pp208 bits: PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 Reset: U U U U U U U U */
 

Definition at line 123 of file asm-m68hc12b/ports.h.

#define PORTS   (*(volatile unsigned char *)0x00D6) /* Port S Data Register pp314 bits: PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 Reset: After reset all bits configured as general­purpose inputs */
 

Definition at line 340 of file asm-m68hc12b/ports.h.

#define PORTT   (*(volatile unsigned char *)0x00AE) /* Timer Port Data Register pp280 bits: PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 275 of file asm-m68hc12b/ports.h.

#define PUCR   (*(volatile unsigned char *)0x000C) /* Pullup Control Register pp140 bits: 0 0 0 PUPE 0 0 PUPB PUPA Reset: 0 0 0 1 0 0 0 0 */
 

Definition at line 37 of file asm-m68hc12b/ports.h.

#define PURDS   (*(volatile unsigned char *)0x00DB) /* Port S Pullup/Reduced Drive Register pp316 bits: 0 RDPS2 RDPS1 RDPS0 0 PUPS2 PUPS1 PUPS0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 346 of file asm-m68hc12b/ports.h.

#define PWCLK   (*(volatile unsigned char *)0x0040) /* PWM Clocks and Concatenate Register pp193 bits: CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 79 of file asm-m68hc12b/ports.h.

#define PWCNT0   (*(volatile unsigned char *)0x0048) /* PWM Channel Counter Register 0 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 95 of file asm-m68hc12b/ports.h.

#define PWCNT1   (*(volatile unsigned char *)0x0049) /* PWM Channel Counter Register 1 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 97 of file asm-m68hc12b/ports.h.

#define PWCNT2   (*(volatile unsigned char *)0x004A) /* PWM Channel Counter Register 2 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 99 of file asm-m68hc12b/ports.h.

#define PWCNT3   (*(volatile unsigned char *)0x004B) /* PWM Channel Counter Register 3 pp201 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 101 of file asm-m68hc12b/ports.h.

#define PWCTL   (*(volatile unsigned char *)0x0054) /* PWM Control Register pp206 bits: 0 0 0 PSWAI CENTR RDPP PUPP PSBCK Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 119 of file asm-m68hc12b/ports.h.

#define PWDTY0   (*(volatile unsigned char *)0x0050) /* PWM Channel Duty Register 0 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 111 of file asm-m68hc12b/ports.h.

#define PWDTY1   (*(volatile unsigned char *)0x0051) /* PWM Channel Duty Register 1 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 113 of file asm-m68hc12b/ports.h.

#define PWDTY2   (*(volatile unsigned char *)0x0052) /* PWM Channel Duty Register 2 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 115 of file asm-m68hc12b/ports.h.

#define PWDTY3   (*(volatile unsigned char *)0x0053) /* PWM Channel Duty Register 3 pp204 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 117 of file asm-m68hc12b/ports.h.

#define PWEN   (*(volatile unsigned char *)0x0042) /* PWM Enable Register pp197 bits: 0 0 0 0 PWEN3 PWEN2 PWEN1 PWEN0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 83 of file asm-m68hc12b/ports.h.

#define PWPER0   (*(volatile unsigned char *)0x004C) /* PWM Channel Period Register 0 pp202 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 103 of file asm-m68hc12b/ports.h.

#define PWPER1   (*(volatile unsigned char *)0x004D) /* PWM Channel Period Register 1 pp202 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 105 of file asm-m68hc12b/ports.h.

#define PWPER2   (*(volatile unsigned char *)0x004E) /* PWM Channel Period Register 2 pp203 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 107 of file asm-m68hc12b/ports.h.

#define PWPER3   (*(volatile unsigned char *)0x004F) /* PWM Channel Period Register 3 pp203 bits: Bit7 6 5 4 3 2 1 0 Reset: 1 1 1 1 1 1 1 1 */
 

Definition at line 109 of file asm-m68hc12b/ports.h.

#define PWPOL   (*(volatile unsigned char *)0x0041) /* PWM Clock Select and Polarity Register pp195 bits: PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 81 of file asm-m68hc12b/ports.h.

#define PWPRES   (*(volatile unsigned char *)0x0043) /* PWM Prescaler Counter Register pp198 bits: 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 85 of file asm-m68hc12b/ports.h.

#define PWSCAL0   (*(volatile unsigned char *)0x0044) /* PWM Scale Register 0 pp199 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 87 of file asm-m68hc12b/ports.h.

#define PWSCAL1   (*(volatile unsigned char *)0x0046) /* PWM Scale Register 1 pp200 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 91 of file asm-m68hc12b/ports.h.

#define PWSCNT0   (*(volatile unsigned char *)0x0045) /* PWM Scale Counter Register 0 pp199 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 89 of file asm-m68hc12b/ports.h.

#define PWSCNT1   (*(volatile unsigned char *)0x0047) /* PWM Scale Counter Register 1 pp200 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 93 of file asm-m68hc12b/ports.h.

#define PWTST   (*(volatile unsigned char *)0x0055) /* PWM Special Mode Register pp207 bits: DISCR DISCP DISCAL 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 121 of file asm-m68hc12b/ports.h.

#define RDRIV   (*(volatile unsigned char *)0x000D) /* Reduced Drive Register pp141 bits: 0 0 0 0 RDPE 0 RDPB RDPA Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 39 of file asm-m68hc12b/ports.h.

#define RTICTL   (*(volatile unsigned char *)0x0014) /* Real­Time Interrupt Control Register pp180 bits: RTIE RSWAI RSBCK 0 RTBYP RTR2 RTR1 RTR0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 51 of file asm-m68hc12b/ports.h.

#define RTIFLG   (*(volatile unsigned char *)0x0015) /* Real­Time Interrupt Flag Register pp181 bits: RTIF 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 53 of file asm-m68hc12b/ports.h.

#define RxFG   (*(volatile unsigned char *)0x0140) /* RECEIVE BUFFER (3) --- SEE 16.4.2 Receive Structures */
 

Definition at line 450 of file asm-m68hc12b/ports.h.

#define SC0BDH   (*(volatile unsigned char *)0x00C0) /* SCI 0 Baud Rate Control Register High pp294 bits: BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 311 of file asm-m68hc12b/ports.h.

#define SC0BDL   (*(volatile unsigned char *)0x00C1) /* SCI 0 Baud Rate Control Register Low pp294 bits: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Reset: 0 0 0 0 0 1 0 0 */
 

Definition at line 313 of file asm-m68hc12b/ports.h.

#define SC0CR1   (*(volatile unsigned char *)0x00C2) /* SCI Control Register 1 pp295 bits: LOOPS WOMS RSRC M WAKE ILT PE PT Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 315 of file asm-m68hc12b/ports.h.

#define SC0CR2   (*(volatile unsigned char *)0x00C3) /* SCI Control Register 2 pp298 bits: TIE TCIE RIE ILIE TE RE RWU SBK Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 317 of file asm-m68hc12b/ports.h.

#define SC0DRH   (*(volatile unsigned char *)0x00C6) /* SCI Data Register High pp302 bits: R8 T8 0 0 0 0 0 0 Reset: U U 0 0 0 0 0 0 */
 

Definition at line 323 of file asm-m68hc12b/ports.h.

#define SC0DRL   (*(volatile unsigned char *)0x00C7) /* SCI Data Register Low pp302 bits: R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Reset: Unaffected by reset */
 

Definition at line 325 of file asm-m68hc12b/ports.h.

#define SC0SR1   (*(volatile unsigned char *)0x00C4) /* SCI Status Register 1 pp299 bits: TDRE TC RDRF IDLE OR NF FE PF Reset: 1 1 0 0 0 0 0 0 */
 

Definition at line 319 of file asm-m68hc12b/ports.h.

#define SC0SR2   (*(volatile unsigned char *)0x00C5) /* SCI Status Register 2 pp301 bits: 0 0 0 0 0 0 0 RAF Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 321 of file asm-m68hc12b/ports.h.

#define SLOW   (*(volatile unsigned char *)0x00E0) /* Slow Mode Divider Register pp179 bits: 0 0 0 0 0 SLDV2 SLDV1 SLDV0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 350 of file asm-m68hc12b/ports.h.

#define SP0BR   (*(volatile unsigned char *)0x00D2) /* SPI Baud Rate Register pp311 bits: 0 0 0 0 0 SPR2 SPR1 SPR0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 333 of file asm-m68hc12b/ports.h.

#define SP0CR1   (*(volatile unsigned char *)0x00D0) /* SPI Control Register 1 pp308 bits: SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 329 of file asm-m68hc12b/ports.h.

#define SP0CR2   (*(volatile unsigned char *)0x00D1) /* SPI Control Register 2 pp310 bits: 0 0 0 0 PUPS RDS 0 SPC0 Reset: 0 0 0 0 1 0 0 0 */
 

Definition at line 331 of file asm-m68hc12b/ports.h.

#define SP0DR   (*(volatile unsigned char *)0x00D5) /* SPI Data Register pp313 bits: Bit7 6 5 4 3 2 1 0 Reset: Unaffected by reset */
 

Definition at line 338 of file asm-m68hc12b/ports.h.

#define SP0SR   (*(volatile unsigned char *)0x00D3) /* SPI Status Register pp312 bits: SPIF WCOL 0 MODF 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 335 of file asm-m68hc12b/ports.h.

#define TC0H   (*(volatile unsigned char *)0x0090) /* Timer Input Capture/Output Compare 0 Register High pp226 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 216 of file asm-m68hc12b/ports.h.

#define TC0H_H   (*(volatile unsigned char *)0x00B8) /* Timer Input Capture Holding Register 0 pp286 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 1 0 0 0 0 0 */
 

Definition at line 295 of file asm-m68hc12b/ports.h.

#define TC0H_L   (*(volatile unsigned char *)0x00B9) /* Timer Input Capture Holding Register 0 pp286 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 297 of file asm-m68hc12b/ports.h.

#define TC0L   (*(volatile unsigned char *)0x0091) /* Timer Input Capture/Output Compare 0 Register Low pp226 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 218 of file asm-m68hc12b/ports.h.

#define TC1H   (*(volatile unsigned char *)0x0092) /* Timer Input Capture/Output Compare 1 Register High pp226 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 220 of file asm-m68hc12b/ports.h.

#define TC1H_H   (*(volatile unsigned char *)0x00BA) /* Timer Input Capture Holding Register 1 pp286 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 299 of file asm-m68hc12b/ports.h.

#define TC1H_L   (*(volatile unsigned char *)0x00BB) /* Timer Input Capture Holding Register 1 pp286 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 301 of file asm-m68hc12b/ports.h.

#define TC1L   (*(volatile unsigned char *)0x0093) /* Timer Input Capture/Output Compare 1 Register Low pp226 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 222 of file asm-m68hc12b/ports.h.

#define TC2H   (*(volatile unsigned char *)0x0094) /* Timer Input Capture/Output Compare 2 Register High pp227 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 224 of file asm-m68hc12b/ports.h.

#define TC2H_H   (*(volatile unsigned char *)0x00BC) /* Timer Input Capture Holding Register 2 pp287 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 303 of file asm-m68hc12b/ports.h.

#define TC2H_L   (*(volatile unsigned char *)0x00BD) /* Timer Input Capture Holding Register 2 pp287 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 305 of file asm-m68hc12b/ports.h.

#define TC2L   (*(volatile unsigned char *)0x0095) /* Timer Input Capture/Output Compare 2 Register Low pp227 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 226 of file asm-m68hc12b/ports.h.

#define TC3H   (*(volatile unsigned char *)0x0096) /* Timer Input Capture/Output Compare 3 Register High pp228 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 228 of file asm-m68hc12b/ports.h.

#define TC3H_H   (*(volatile unsigned char *)0x00BE) /* Timer Input Capture Holding Register 3 pp287 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 307 of file asm-m68hc12b/ports.h.

#define TC3H_L   (*(volatile unsigned char *)0x00BF) /* Timer Input Capture Holding Register 3 pp287 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 309 of file asm-m68hc12b/ports.h.

#define TC3L   (*(volatile unsigned char *)0x0097) /* Timer Input Capture/Output Compare 3 Register Low pp228 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 230 of file asm-m68hc12b/ports.h.

#define TC4H   (*(volatile unsigned char *)0x0098) /* Timer Input Capture/Output Compare 4 Register High pp228 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 232 of file asm-m68hc12b/ports.h.

#define TC4L   (*(volatile unsigned char *)0x0099) /* Timer Input Capture/Output Compare 4 Register Low pp228 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 234 of file asm-m68hc12b/ports.h.

#define TC5H   (*(volatile unsigned char *)0x009A) /* Timer Input Capture/Output Compare 5 Register High pp228 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 236 of file asm-m68hc12b/ports.h.

#define TC5L   (*(volatile unsigned char *)0x009B) /* Timer Input Capture/Output Compare 5 Register Low pp228 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 238 of file asm-m68hc12b/ports.h.

#define TC6H   (*(volatile unsigned char *)0x009C) /* Timer Input Capture/Output Compare 6 Register High pp229 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 240 of file asm-m68hc12b/ports.h.

#define TC6L   (*(volatile unsigned char *)0x009D) /* Timer Input Capture/Output Compare 6 Register Low pp229 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 242 of file asm-m68hc12b/ports.h.

#define TC7H   (*(volatile unsigned char *)0x009E) /* Timer Input Capture/Output Compare 7 Register High pp229 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 244 of file asm-m68hc12b/ports.h.

#define TC7L   (*(volatile unsigned char *)0x009F) /* Timer Input Capture/Output Compare 7 Register Low pp229 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 246 of file asm-m68hc12b/ports.h.

#define TCNTH   (*(volatile unsigned char *)0x0084) /* Timer Count Register High pp218 bits: Bit15 14 13 12 11 10 9 8 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 193 of file asm-m68hc12b/ports.h.

#define TCNTL   (*(volatile unsigned char *)0x0085) /* Timer Count Register Low pp218 bits: Bit7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 195 of file asm-m68hc12b/ports.h.

#define TCTL1   (*(volatile unsigned char *)0x0088) /* Timer Control Register 1 pp220 bits: OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 200 of file asm-m68hc12b/ports.h.

#define TCTL2   (*(volatile unsigned char *)0x0089) /* Timer Control Register 2 pp220 bits: OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 202 of file asm-m68hc12b/ports.h.

#define TCTL3   (*(volatile unsigned char *)0x008A) /* Timer Control Register 3 pp221 bits: EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 204 of file asm-m68hc12b/ports.h.

#define TCTL4   (*(volatile unsigned char *)0x008B) /* Timer Control Register 4 pp221 bits: EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 206 of file asm-m68hc12b/ports.h.

#define TFLG1   (*(volatile unsigned char *)0x008E) /* Timer Interrupt Flag Register 1 pp224 bits: C7F C6F C5F C4F C3F C2F C1F C0F Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 212 of file asm-m68hc12b/ports.h.

#define TFLG2   (*(volatile unsigned char *)0x008F) /* Timer Interrupt Flag Register 2 pp225 bits: TOF 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 214 of file asm-m68hc12b/ports.h.

#define TIMTST   (*(volatile unsigned char *)0x00AD) /* Timer Test Register pp279 bits: 0 0 0 0 0 0 TCBYP PCBYP (1) Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 273 of file asm-m68hc12b/ports.h.

#define TIOS   (*(volatile unsigned char *)0x0080) /* Timer IC/OC Select Register pp216 bits: IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 185 of file asm-m68hc12b/ports.h.

#define TMSK1   (*(volatile unsigned char *)0x008C) /* Timer Mask Register 1 pp222 bits: C7I C6I C5I C4I C3I C2I C1I C0I Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 208 of file asm-m68hc12b/ports.h.

#define TMSK2   (*(volatile unsigned char *)0x008D) /* Timer Mask Register 2 pp223 bits: TOI 0 PUPT RDPT TCRE PR2 PR1 PR0 Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 210 of file asm-m68hc12b/ports.h.

#define TSCR   (*(volatile unsigned char *)0x0086) /* Timer System Control Register pp219 bits: TEN TSWAI TSBCK TFFCA Reset: 0 0 0 0 0 0 0 0 */
 

Definition at line 197 of file asm-m68hc12b/ports.h.


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