00001 00009 /* SCI.H CONFIG START */ 00010 /*#define SCI0_BAUD 9600L*/ 00011 /*#define SCI1_BAUD 9600L*/ 00012 #define SCI0 00013 /*#define SCI1*/ 00014 /* SCI.H CONFIG END */ 00015 00016 # ifdef SCI0 00017 __inline__ extern void sci0_init(ushort baud); 00018 # endif 00019 # ifdef SCI1 00020 __inline__ extern void sci1_init(ushort baud); 00021 # endif 00022 extern char sci_rx_poll(unsigned char *sci_base); 00023 extern void sci_tx_flush(unsigned char *sci_base); 00024 extern void sci_tx(unsigned char *sci_base, char data); 00025 extern char sci_rx(unsigned char *sci_base, char data); 00026 /* Register offsets: derived from pp15. */ 00027 #define SCIBDH 0 /* SCI Baud Rate Register High Read/Write */ 00028 #define SCIBDL 1 /* SCI Baud Rate Register Low Read/Write */ 00029 #define SCICR1 2 /* SCI Control Register1 Read/Write */ 00030 #define SCICR2 3 /* SCI Control Register 2 Read/Write */ 00031 #define SCISR1 4 /* SCI Status Register 1 Read */ 00032 #define SCISR2 5 /* SCI Status Register 2 Read/Write */ 00033 #define SCIDRH 6 /* SCI Data Register High Read/Write */ 00034 #define SCIDRL 7 /* SCI Data Register Low Read/Write */ 00035 00036 /* <tt> 00037 * SBR[15:0] aka SCIBDH/SCIBDL (SCI Baude Rate register, from pp17) 00038 * bit name normal descr. 00039 * ------------------------------- 00040 * 15w IREN 0 Infrared mod. enable. 00041 * 14:13w TNP 0 Transmit pulse width. 00042 * 12:0w SBR xxxx SCI Baude Rate (see below 00043 * When IREN=0 then, SCI baud rate = SCI module clock / (16 x SBR[12:0]) 00044 * When IREN=1 then, SCI baud rate = SCI module clock / (32 x SBR[12:1]) 00045 * 00046 * SCICR1 (SCI Control Register 1, from pp18) 00047 * bit name normal descr. 00048 * --------------------------- 00049 * 7w - LOOPS 0 Internal loopback config 00050 * 6w - SCISWAI 0 Stop in WAIt mode 00051 * 5w - RSRC 0 Reciever source bit for LOOPS mode 00052 * 4w - M 0 Mode: 8 bits (0) or 9 bits (1); both with 1 stop bit 00053 * 3w - WAKE 0 Wakeup condition: Idle line (0) or addr. mark (1) 00054 * 2w - ILT x Idle line type: start after start bit (0) or stop (1) 00055 * 1w - PE x Parity enable 00056 * 0w - PT x Parity type: even (0) or odd (1) 00057 * 00058 * SCICR2 (SCI Control Register 2, from pp20) 00059 * bit name normal descr. 00060 * 7w - TIE x Transmit Interrupt Enable for TDRE (TX data reg. empty) 00061 * 6w - TCIE x Transmit Complete Interrupte Enable 00062 * 5w - RIE x Reciever full Interrupt Enable for RDRF (RX data reg. full) 00063 * 4w - ILIE x Idle Line Interrupt Enable 00064 * 3w - TE x Transmit Enable 00065 * 2w - RE x Receiver Enable 00066 * 1w - RWU 0 Receiver WakeUp 00067 * 0w - SBK 0 Send Break 00068 * 00069 * SCISR1 (SCI Status Register 1, from pp21). 00070 * bit name normal descr. 00071 * 7r - TDRE TX Data Register Empty 00072 * 6r - TC TX Complete 00073 * 5r - RDRF RX Data Register Full 00074 * 4r - IDLE Idle line flag; 10/11 idle bits detected 00075 * 3r - OR OverRun flag; unable to latch-out bits in RX shift register 00076 * 2r - NF Noise Flag 00077 * 1r - FE Framing Error; incorrect stop bit detected 00078 * 0r - PF Parity Error Flag 00079 * 00080 * SCISR2 (SCI Status Register 2, from pp23). 00081 * bit name normal descr. 00082 * 2w - BRK13 0 Set break char. len. to 10/11 bits (0) OR 13/14 bits (1) {depends on SCICR1[M]} 00083 * 1w - TXDIR x Single wire TX pin direction; in (0) or out (1) 00084 * 0r - RAP x Receiver Active; If (1), then reception is in progress. 00085 * </tt> 00086 * 00087 * SCIDRH (SCI Data Register High). 00088 * bit name normal descr. 00089 * 7r R8 9th RX bit for 9bit data mode 00090 * 6w T8 9th TX bit for 9bit data mode 00091 * SCIDRL (SCI Data Register Low) - read for RX'd data; write to queue TX. 00092 */ 00093 00094 /* Bit masks for the 9S12 SCI */ 00095 /*SCIBDH*/ 00096 #define SCI_IREN 0x80 00097 #define SCI_TNP1 0x40 00098 #define SCI_TNP0 0x20 00099 /*SCICR1*/ 00100 #define SCI_LOOPS 0x80 00101 #define SCI_SWAI 0x40 00102 #define SCI_RSRC 0x20 00103 #define SCI_M 0x10 00104 #define SCI_WAKE 0x08 00105 #define SCI_ILT 0x04 00106 #define SCI_PE 0x02 00107 #define SCI_PT 0x01 00108 /*SCICR2*/ 00109 #define SCI_TIE 0x80 00110 #define SCI_TCIE 0x40 00111 #define SCI_RIE 0x20 00112 #define SCI_ILIE 0x10 00113 #define SCI_TE 0x08 00114 #define SCI_RE 0x04 00115 #define SCI_RWU 0x02 00116 #define SCI_SBK 0x01 00117 /*SCISR1*/ 00118 #define SCI_TDRE 0x80 00119 #define SCI_TC 0x40 00120 #define SCI_RDRF 0x20 00121 #define SCI_IDLE 0x10 00122 #define SCI_OR 0x08 00123 #define SCI_NF 0x04 00124 #define SCI_FE 0x02 00125 #define SCI_PF 0x01 00126 /*SCISR2*/ 00127 #define SCI_BRK13 0x04 00128 #define SCI_TXDIR 0x02 00129 #define SCI_RAP 0x01
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