BeeOS: vectors.h Source File

00001 
00012 /*  0xEF80 - 0xEF8B: Reserved. */
00013 #define VEC_TABLE           (*(volatile void *) 0xEF8C)
00014 #define VEC_PWM_SHUTDOWN    (*(volatile void *) 0xEF8C) /* PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C */
00015 #define VEC_PTP             (*(volatile void *) 0xEF8E) /* Port P Interrupt I-Bit PTPIF (PTPIE) $8E */
00016 #define VEC_CAN4_TX         (*(volatile void *) 0xEF90) /* CAN4 transmit I-Bit CAN4TIER (TXEIE2-TXEIE0) $90 */
00017 #define VEC_CAN4_RX         (*(volatile void *) 0xEF92) /* CAN4 receive I-Bit CAN4RIER (RXFIE) $92 */
00018 #define VEC_CAN4_ERR        (*(volatile void *) 0xEF94) /* CAN4 errors I-Bit CAN4RIER (CSCIE, OVRIE) $94 */
00019 #define VEC_CAN4_WAKE       (*(volatile void *) 0xEF96) /* CAN4 wake-up I-Bit CAN4RIER (WUPIE) $96 */
00020 #define VEC_CAN3_TX         (*(volatile void *) 0xEF98) /* CAN3 transmit I-Bit CAN3TIER (TXEIE2-TXEIE0) $98 */
00021 #define VEC_CAN3_RX         (*(volatile void *) 0xEF9A) /* CAN3 receive I-Bit CAN3RIER (RXFIE) $9A */
00022 #define VEC_CAN3_ERR        (*(volatile void *) 0xEF9C) /* CAN3 errors I-Bit CAN3RIER (TXEIE2-TXEIE0) $9C */
00023 #define VEC_CAN3_WAKE       (*(volatile void *) 0xEF9E) /* CAN3 wake-up I-Bit CAN3RIER (WUPIE) $9E */
00024 #define VEC_CAN2_TX         (*(volatile void *) 0xEFA0) /* CAN2 transmit I-Bit CAN2TIER (TXEIE2-TXEIE0) $A0 */
00025 #define VEC_CAN2_RX         (*(volatile void *) 0xEFA2) /* CAN2 receive I-Bit CAN2RIER (RXFIE) $A2 */
00026 #define VEC_CAN2_ERR        (*(volatile void *) 0xEFA4) /* CAN2 errors I-Bit CAN2RIER (CSCIE, OVRIE) $A4 */
00027 #define VEC_CAN2_WAKE       (*(volatile void *) 0xEFA6) /* CAN2 wake-up I-Bit CAN2RIER (WUPIE) $A6 */
00028 #define VEC_CAN1_TX         (*(volatile void *) 0xEFA8) /* CAN1 transmit I-Bit CAN1TIER (TXEIE2-TXEIE0) $A8 */
00029 #define VEC_CAN1_RX         (*(volatile void *) 0xEFAA) /* CAN1 receive I-Bit CAN1RIER (RXFIE) $AA */
00030 #define VEC_CAN1_ERR        (*(volatile void *) 0xEFAC) /* CAN1 errors I-Bit CAN1RIER (CSCIE, OVRIE) $AC */
00031 #define VEC_CAN1_WAKE       (*(volatile void *) 0xEFAE) /* CAN1 wake-up I-Bit CAN1RIER (WUPIE) $AE */
00032 #define VEC_CAN0_TX         (*(volatile void *) 0xEFB0) /* CAN0 transmit I-Bit CAN0TIER (TXEIE2-TXEIE0) $B0 */
00033 #define VEC_CAN0_RX         (*(volatile void *) 0xEFB2) /* CAN0 receive I-Bit CAN0RIER (RXFIE) $B2 */
00034 #define VEC_CAN0_ERR        (*(volatile void *) 0xEFB4) /* CAN0 errors I-Bit CAN0RIER (CSCIE, OVRIE) $B4 */
00035 #define VEC_CAN0_WAKE       (*(volatile void *) 0xEFB6) /* CAN0 wake-up I-Bit CAN0RIER (WUPIE) $B6 */
00036 #define VEC_FLASH           (*(volatile void *) 0xEFB8) /* FLASH I-Bit FCTL(CCIE, CBEIE) $B8 */
00037 #define VEC_EEPROM          (*(volatile void *) 0xEFBA) /* EEPROM I-Bit EECTL(CCIE, CBEIE) $BA */
00038 #define VEC_SPI2            (*(volatile void *) 0xEFBC) /* SPI2 I-Bit SP2CR1 (SPIE, SPTIE) $BC */
00039 #define VEC_SPI1            (*(volatile void *) 0xEFBE) /* SPI1 I-Bit SP1CR1 (SPIE, SPTIE) $BE */
00040 #define VEC_IIC             (*(volatile void *) 0xEFC0) /* IIC Bus I-Bit IBCR (IBIE) $C0 */
00041 #define VEC_BDLC            (*(volatile void *) 0xEFC2) /* BDLC I-Bit DLCBCR1(IE) $C2 */
00042 #define VEC_CRG_SELFCLK_MODE    (*(volatile void *) 0xEFC4) /* CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4 */
00043 #define VEC_CRG_PLL_LOCK    (*(volatile void *) 0xEFC6) /* CRG PLL lock I-Bit CRGINT(LOCKIE) $C6 */
00044 #define VEC_ACC_B_OVERFLOW  (*(volatile void *) 0xEFC8) /* Pulse Accumulator B Overflow I-Bit PBCTL(PBOVI) $C8 */
00045 #define VEC_MODCOUNT_UNDERFLOW  (*(volatile void *) 0xEFCA) /* Modulus Down Counter underflow I-Bit MCCTL(MCZI) $CA */
00046 #define VEC_PTH             (*(volatile void *) 0xEFCC) /* Port H I-Bit PTHIF(PTHIE) $CC */
00047 #define VEC_PTJ             (*(volatile void *) 0xEFCE) /* Port J I-Bit PTJIF (PTJIE) $CE */
00048 #define VEC_ATD1            (*(volatile void *) 0xEFD0) /* ATD1 I-Bit ATD1CTL2 (ASCIE) $D0 */
00049 #define VEC_ATD0            (*(volatile void *) 0xEFD2) /* ATD0 I-Bit ATD0CTL2 (ASCIE) $D2 */
00050 #define VEC_SCI1            (*(volatile void *) 0xEFD4) /* SCI1 I-Bit SC1CR2 (TIE, TCIE, RIE, ILIE) $D4 */
00051 #define VEC_SCI0            (*(volatile void *) 0xEFD6) /* SCI0 I-Bit SC0CR2 (TIE, TCIE, RIE, ILIE) $D6 */
00052 #define VEC_SPI0            (*(volatile void *) 0xEFD8) /* SPI0 I-Bit SP0CR1 (SPIE, SPTIE) $D8 */
00053 #define VEC_ACC_INPUT_EDGE  (*(volatile void *) 0xEFDA) /* Pulse accumulator input edge I-Bit PACTL (PAI) $DA */
00054 #define VEC_ACC_A_OVERFLOW  (*(volatile void *) 0xEFDC) /* Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC */
00055 #define VEC_ECT_OVERFLOW    (*(volatile void *) 0xEFDE) /* Enhanced Capture Timer overflow I-Bit TSRC2 (TOF) $DE */
00056 #define VEC_ECT7            (*(volatile void *) 0xEFE0) /* Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0 */
00057 #define VEC_ECT6            (*(volatile void *) 0xEFE2) /* Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2 */
00058 #define VEC_ECT5            (*(volatile void *) 0xEFE4) /* Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4 */
00059 #define VEC_ECT4            (*(volatile void *) 0xEFE6) /* Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6 */
00060 #define VEC_ECT3            (*(volatile void *) 0xEFE8) /* Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8 */
00061 #define VEC_ECT2            (*(volatile void *) 0xEFEA) /* Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA */
00062 #define VEC_ECT1            (*(volatile void *) 0xEFEC) /* Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC */
00063 #define VEC_ECT0            (*(volatile void *) 0xEFEE) /* Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE */
00064 #define VEC_RTI             (*(volatile void *) 0xEFF0) /* Real Time Interrupt I-Bit CRGINT (RTIE) $F0 */
00065 #define VEC_IRQ             (*(volatile void *) 0xEFF2) /* IRQ I-Bit IRQCR (IRQEN) $F2 */
00066 #define VEC_XIRQ            (*(volatile void *) 0xEFF4) /* XIRQ X-Bit None  */
00067 #define VEC_SWI             (*(volatile void *) 0xEFF6) /* SWI None None  */
00068 #define VEC_ILLEGAL_OP      (*(volatile void *) 0xEFF8) /* Unimplemented instruction trap None None  */
00069 #define VEC_COP_FAIL        (*(volatile void *) 0xEFFA) /* COP failure reset None COP rate select  */
00070 #define VEC_COP_CLK         (*(volatile void *) 0xEFFC) /* Clock Monitor fail reset None PLLCTL (CME, SCME)  */
00071 #define VEC_RESET           (*(volatile void *) 0xEFFE) /* Reset None None  */
00072 
00073 typedef enum {          /*  0xEF80 - 0xFF8B: Reserved. */
00076     INTRID_PWM_SHUTDOWN = 6,    /* 0xEF8C PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C */
00077     INTRID_PTP,         /* 0xEF8E */
00078     INTRID_CAN4_TX,     /* 0xEF90 */
00079     INTRID_CAN4_RX,     /* 0xEF92 */
00080     INTRID_CAN4_ERR,    /* 0xEF94 */
00081     INTRID_CAN4_WAKE,   /* 0xEF96 */
00082     INTRID_CAN3_TX,     /* 0xEF98 */
00083     INTRID_CAN3_RX,     /* 0xEF9A */
00084     INTRID_CAN3_ERR,    /* 0xEF9C */
00085     INTRID_CAN3_WAKE,   /* 0xEF9E */
00086     INTRID_CAN2_TX,     /* 0xEFA0 */
00087     INTRID_CAN2_RX,     /* 0xEFA2 */
00088     INTRID_CAN2_ERR,    /* 0xEFA4 */
00089     INTRID_CAN2_WAKE,   /* 0xEFA6 */
00090     INTRID_CAN1_TX,     /* 0xEFA8 */
00091     INTRID_CAN1_RX,     /* 0xEFAA */
00092     INTRID_CAN1_ERR,    /* 0xEFAC */
00093     INTRID_CAN1_WAKE,   /* 0xEFAE */
00094     INTRID_CAN0_TX,     /* 0xEFB0 */
00095     INTRID_CAN0_RX,     /* 0xEFB2 */
00096     INTRID_CAN0_ERR,    /* 0xEFB4 */
00097     INTRID_CAN0_WAKE,   /* 0xEFB6 */
00098     INTRID_FLASH,       /* 0xEFB8 */
00099     INTRID_EEPROM,      /* 0xEFBA */
00100     INTRID_SPI2,        /* 0xEFBC */
00101     INTRID_SPI1,        /* 0xEFBE */
00102     INTRID_IIC,         /* 0xEFC0 */
00103     INTRID_BDLC,        /* 0xEFC2 */
00104     INTRID_CRG_SELFCLK_MODE,    /* 0xEFC4 */
00105     INTRID_CRG_PLL_LOCK,    /* 0xEFC6 */
00106     INTRID_ACC_B_OVERFLOW,  /* 0xEFC8 */
00107     INTRID_MODCOUNT_UNDERFLOW,  /* 0xEFCA */
00108     INTRID_PTH,         /* 0xEFCC */
00109     INTRID_PTJ,         /* 0xEFCE */
00110     INTRID_ATD1,        /* 0xEFD0 */
00111     INTRID_ATD0,        /* 0xEFD2 */
00112     INTRID_SCI1,        /* 0xEFD4 */
00113     INTRID_SCI0,        /* 0xEFD6 */
00114     INTRID_SPI0,        /* 0xEFD8 */
00115     INTRID_ACC_INPUT_EDGE,  /* 0xEFDA */
00116     INTRID_ACC_A_OVERFLOW,  /* 0xEFDC */
00117     INTRID_ECT_OVERFLOW,/* 0xEFDE Enhanced Capture Timer overflow I-Bit TSRC2 (TOF) $DE */
00118     INTRID_ECT7,        /* 0xEFE0 */
00119     INTRID_ECT6,        /* 0xEFE2 */
00120     INTRID_ECT5,        /* 0xEFE4 */
00121     INTRID_ECT4,        /* 0xEFE6 */
00122     INTRID_ECT3,        /* 0xEFE8 */
00123     INTRID_ECT2,        /* 0xEFEA */
00124     INTRID_ECT1,        /* 0xEFEC */
00125     INTRID_ECT0,        /* 0xEFEE */
00126     INTRID_RTI,         /* 0xEFF0 */
00127     INTRID_IRQ,         /* 0xEFF2 */
00128     INTRID_XIRQ,        /* 0xEFF4 */
00129     INTRID_SWI,         /* 0xEFF6 */
00130     INTRID_ILLEGAL_OP,  /* 0xEFF8 */
00131     INTRID_COP_FAIL,    /* 0xEFFA */
00132     INTRID_COP_CLK,     /* 0xEFFC Clock Monitor fail reset None PLLCTL (CME, SCME)  */
00133     INTRID_RESET,       /* 0xEFFE */
00134     INTRID_MAX
00135 } intrid_t;