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Defines |
| #define | VEC_TABLE (*(volatile ushort *) 0xFF8C) |
| #define | VEC_PWM_SHUTDOWN (*(volatile ushort *) 0xFF8C) /* PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C */ |
| #define | VEC_PTP (*(volatile ushort *) 0xFF8E) /* Port P Interrupt I-Bit PTPIF (PTPIE) $8E */ |
| #define | VEC_CAN4_TX (*(volatile ushort *) 0xFF90) /* CAN4 transmit I-Bit CAN4TIER (TXEIE2-TXEIE0) $90 */ |
| #define | VEC_CAN4_RX (*(volatile ushort *) 0xFF92) /* CAN4 receive I-Bit CAN4RIER (RXFIE) $92 */ |
| #define | VEC_CAN4_ERR (*(volatile ushort *) 0xFF94) /* CAN4 errors I-Bit CAN4RIER (CSCIE, OVRIE) $94 */ |
| #define | VEC_CAN4_WAKE (*(volatile ushort *) 0xFF96) /* CAN4 wake-up I-Bit CAN4RIER (WUPIE) $96 */ |
| #define | VEC_CAN3_TX (*(volatile ushort *) 0xFF98) /* CAN3 transmit I-Bit CAN3TIER (TXEIE2-TXEIE0) $98 */ |
| #define | VEC_CAN3_RX (*(volatile ushort *) 0xFF9A) /* CAN3 receive I-Bit CAN3RIER (RXFIE) $9A */ |
| #define | VEC_CAN3_ERR (*(volatile ushort *) 0xFF9C) /* CAN3 errors I-Bit CAN3RIER (TXEIE2-TXEIE0) $9C */ |
| #define | VEC_CAN3_WAKE (*(volatile ushort *) 0xFF9E) /* CAN3 wake-up I-Bit CAN3RIER (WUPIE) $9E */ |
| #define | VEC_CAN2_TX (*(volatile ushort *) 0xFFA0) /* CAN2 transmit I-Bit CAN2TIER (TXEIE2-TXEIE0) $A0 */ |
| #define | VEC_CAN2_RX (*(volatile ushort *) 0xFFA2) /* CAN2 receive I-Bit CAN2RIER (RXFIE) $A2 */ |
| #define | VEC_CAN2_ERR (*(volatile ushort *) 0xFFA4) /* CAN2 errors I-Bit CAN2RIER (CSCIE, OVRIE) $A4 */ |
| #define | VEC_CAN2_WAKE (*(volatile ushort *) 0xFFA6) /* CAN2 wake-up I-Bit CAN2RIER (WUPIE) $A6 */ |
| #define | VEC_CAN1_TX (*(volatile ushort *) 0xFFA8) /* CAN1 transmit I-Bit CAN1TIER (TXEIE2-TXEIE0) $A8 */ |
| #define | VEC_CAN1_RX (*(volatile ushort *) 0xFFAA) /* CAN1 receive I-Bit CAN1RIER (RXFIE) $AA */ |
| #define | VEC_CAN1_ERR (*(volatile ushort *) 0xFFAC) /* CAN1 errors I-Bit CAN1RIER (CSCIE, OVRIE) $AC */ |
| #define | VEC_CAN1_WAKE (*(volatile ushort *) 0xFFAE) /* CAN1 wake-up I-Bit CAN1RIER (WUPIE) $AE */ |
| #define | VEC_CAN0_TX (*(volatile ushort *) 0xFFB0) /* CAN0 transmit I-Bit CAN0TIER (TXEIE2-TXEIE0) $B0 */ |
| #define | VEC_CAN0_RX (*(volatile ushort *) 0xFFB2) /* CAN0 receive I-Bit CAN0RIER (RXFIE) $B2 */ |
| #define | VEC_CAN0_ERR (*(volatile ushort *) 0xFFB4) /* CAN0 errors I-Bit CAN0RIER (CSCIE, OVRIE) $B4 */ |
| #define | VEC_CAN0_WAKE (*(volatile ushort *) 0xFFB6) /* CAN0 wake-up I-Bit CAN0RIER (WUPIE) $B6 */ |
| #define | VEC_FLASH (*(volatile ushort *) 0xFFB8) /* FLASH I-Bit FCTL(CCIE, CBEIE) $B8 */ |
| #define | VEC_EEPROM (*(volatile ushort *) 0xFFBA) /* EEPROM I-Bit EECTL(CCIE, CBEIE) $BA */ |
| #define | VEC_SPI2 (*(volatile ushort *) 0xFFBC) /* SPI2 I-Bit SP2CR1 (SPIE, SPTIE) $BC */ |
| #define | VEC_SPI1 (*(volatile ushort *) 0xFFBE) /* SPI1 I-Bit SP1CR1 (SPIE, SPTIE) $BE */ |
| #define | VEC_IIC (*(volatile ushort *) 0xFFC0) /* IIC Bus I-Bit IBCR (IBIE) $C0 */ |
| #define | VEC_BDLC (*(volatile ushort *) 0xFFC2) /* BDLC I-Bit DLCBCR1(IE) $C2 */ |
| #define | VEC_CRG_SELFCLK_MODE (*(volatile ushort *) 0xFFC4) /* CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4 */ |
| #define | VEC_CRG_PLL_LOCK (*(volatile ushort *) 0xFFC6) /* CRG PLL lock I-Bit CRGINT(LOCKIE) $C6 */ |
| #define | VEC_ACC_B_OVERFLOW (*(volatile ushort *) 0xFFC8) /* Pulse Accumulator B Overflow I-Bit PBCTL(PBOVI) $C8 */ |
| #define | VEC_MODCOUNT_UNDERFLOW (*(volatile ushort *) 0xFFCA) /* Modulus Down Counter underflow I-Bit MCCTL(MCZI) $CA */ |
| #define | VEC_PTH (*(volatile ushort *) 0xFFCC) /* Port H I-Bit PTHIF(PTHIE) $CC */ |
| #define | VEC_PTJ (*(volatile ushort *) 0xFFCE) /* Port J I-Bit PTJIF (PTJIE) $CE */ |
| #define | VEC_ATD1 (*(volatile ushort *) 0xFFD0) /* ATD1 I-Bit ATD1CTL2 (ASCIE) $D0 */ |
| #define | VEC_ATD0 (*(volatile ushort *) 0xFFD2) /* ATD0 I-Bit ATD0CTL2 (ASCIE) $D2 */ |
| #define | VEC_SCI1 (*(volatile ushort *) 0xFFD4) /* SCI1 I-Bit SC1CR2 (TIE, TCIE, RIE, ILIE) $D4 */ |
| #define | VEC_SCI0 (*(volatile ushort *) 0xFFD6) /* SCI0 I-Bit SC0CR2 (TIE, TCIE, RIE, ILIE) $D6 */ |
| #define | VEC_SPI0 (*(volatile ushort *) 0xFFD8) /* SPI0 I-Bit SP0CR1 (SPIE, SPTIE) $D8 */ |
| #define | VEC_ACC_INPUT_EDGE (*(volatile ushort *) 0xFFDA) /* Pulse accumulator input edge I-Bit PACTL (PAI) $DA */ |
| #define | VEC_ACC_A_OVERFLOW (*(volatile ushort *) 0xFFDC) /* Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC */ |
| #define | VEC_ECT_OVERFLOW (*(volatile ushort *) 0xFFDE) /* Enhanced Capture Timer overflow I-Bit TSRC2 (TOF) $DE */ |
| #define | VEC_ECT7 (*(volatile ushort *) 0xFFE0) /* Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0 */ |
| #define | VEC_ECT6 (*(volatile ushort *) 0xFFE2) /* Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2 */ |
| #define | VEC_ECT5 (*(volatile ushort *) 0xFFE4) /* Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4 */ |
| #define | VEC_ECT4 (*(volatile ushort *) 0xFFE6) /* Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6 */ |
| #define | VEC_ECT3 (*(volatile ushort *) 0xFFE8) /* Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8 */ |
| #define | VEC_ECT2 (*(volatile ushort *) 0xFFEA) /* Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA */ |
| #define | VEC_ECT1 (*(volatile ushort *) 0xFFEC) /* Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC */ |
| #define | VEC_ECT0 (*(volatile ushort *) 0xFFEE) /* Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE */ |
| #define | VEC_RTI (*(volatile ushort *) 0xFFF0) /* Real Time Interrupt I-Bit CRGINT (RTIE) $F0 */ |
| #define | VEC_IRQ (*(volatile ushort *) 0xFFF2) /* IRQ I-Bit IRQCR (IRQEN) $F2 */ |
| #define | VEC_XIRQ (*(volatile ushort *) 0xFFF4) /* XIRQ X-Bit None */ |
| #define | VEC_SWI (*(volatile ushort *) 0xFFF6) /* SWI None None */ |
| #define | VEC_ILLEGAL_OP (*(volatile ushort *) 0xFFF8) /* Unimplemented instruction trap None None */ |
| #define | VEC_COP_FAIL (*(volatile ushort *) 0xFFFA) /* COP failure reset None COP rate select */ |
| #define | VEC_COP_CLK (*(volatile ushort *) 0xFFFC) /* Clock Monitor fail reset None PLLCTL (CME, SCME) */ |
| #define | VEC_RESET (*(volatile ushort *) 0xFFFE) /* Reset None None */ |
Enumerations |
| enum | intrid_t {
INTRID_PWM_SHUTDOWN = 6,
INTRID_PTP,
INTRID_CAN4_TX,
INTRID_CAN4_RX,
INTRID_CAN4_ERR,
INTRID_CAN4_WAKE,
INTRID_CAN3_TX,
INTRID_CAN3_RX,
INTRID_CAN3_ERR,
INTRID_CAN3_WAKE,
INTRID_CAN2_TX,
INTRID_CAN2_RX,
INTRID_CAN2_ERR,
INTRID_CAN2_WAKE,
INTRID_CAN1_TX,
INTRID_CAN1_RX,
INTRID_CAN1_ERR,
INTRID_CAN1_WAKE,
INTRID_CAN0_TX,
INTRID_CAN0_RX,
INTRID_CAN0_ERR,
INTRID_CAN0_WAKE,
INTRID_FLASH,
INTRID_EEPROM,
INTRID_SPI2,
INTRID_SPI1,
INTRID_IIC,
INTRID_BDLC,
INTRID_CRG_SELFCLK_MODE,
INTRID_CRG_PLL_LOCK,
INTRID_ACC_B_OVERFLOW,
INTRID_MODCOUNT_UNDERFLOW,
INTRID_PTH,
INTRID_PTJ,
INTRID_ATD1,
INTRID_ATD0,
INTRID_SCI1,
INTRID_SCI0,
INTRID_SPI0,
INTRID_ACC_INPUT_EDGE,
INTRID_ACC_A_OVERFLOW,
INTRID_ECT_OVERFLOW,
INTRID_ECT7,
INTRID_ECT6,
INTRID_ECT5,
INTRID_ECT4,
INTRID_ECT3,
INTRID_ECT2,
INTRID_ECT1,
INTRID_ECT0,
INTRID_RTI,
INTRID_IRQ,
INTRID_XIRQ,
INTRID_SWI,
INTRID_ILLEGAL_OP,
INTRID_COP_FAIL,
INTRID_COP_CLK,
INTRID_RESET,
INTRID_MAX
} |
1.3.6-20040222