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vectors.h File Reference

Detailed Description

Provides access to interrupt vectors to assign ISRs.

Generated from the "M68HC12B Family Technical Data M68HC12B/D Rev. 4, 4/2002" M68HC12B.pdf by Motorola, Inc. pp106 by Paul Harvey, 2004/03. NB: Could not use new editions of this datasheet due to PDF encryption or other "feature" that prevented pstotext(1) from working.

Note:
For MC68HC(9)12BC32 devices, please ensure MC68HC12BC32 is defined in this file.
See also:
asm-m68hc12b/ports.h

Definition in file m68hc12b/vectors.h.

Go to the source code of this file.

Defines

#define VEC_CAN_TX   (*(volatile void *) 0xFFC4) /* MSCAN transmit I bit CTCR TXEIE[2:0] $C4 */
#define VEC_CAN_RX   (*(volatile void *) 0xFFC6) /* MSCAN receive I bit CRIER RXFIE $C6 */
#define VEC_CAN_ERR   (*(volatile void *) 0xFFC8) /* MSCAN errors I bit CRIER - RWRNIE, TWRNIE, RERRIE, TERRIE, BOFFIE, OVRIE $C8 */
#define VEC_CAN_WAKE   (*(volatile void *) 0xFFD0) /* MSCAN wakeup I bit CRIER WUPIE $D0 */
#define VEC_ATD   (*(volatile void *) 0xFFD2) /* ATD I bit ATDCTL2 ASCIE $D2 */
#define VEC_SCI   (*(volatile void *) 0xFFD6) /* SCI 0 I bit SC0CR2 TIE, TCIE, RIE, ILIE $D6 */
#define VEC_SPI   (*(volatile void *) 0xFFD8) /* SPI serial transfer complete I bit SP0CR1 SPIE $D8 */
#define VEC_ACC_INPUT_EDGE   (*(volatile void *) 0xFFDA) /* Pulse accumulator input edge I bit PACTL PAI $DA */
#define VEC_ACC_OVERFLOW   (*(volatile void *) 0xFFDC) /* Pulse accumulator overflow I bit PACTL PAOVI $DC */
#define VEC_TMR_OVERFLOW   (*(volatile void *) 0xFFDE) /* Timer overflow I bit TMSK2 TOI $DE */
#define VEC_TMR7   (*(volatile void *) 0xFFE0) /* Timer channel 7 I bit TMSK1 C7I $E0 */
#define VEC_TMR6   (*(volatile void *) 0xFFE2) /* Timer channel 6 I bit TMSK1 C6I $E2 */
#define VEC_TMR5   (*(volatile void *) 0xFFE4) /* Timer channel 5 I bit TMSK1 C5I $E4 */
#define VEC_TMR4   (*(volatile void *) 0xFFE6) /* Timer channel 4 I bit TMSK1 C4I $E6 */
#define VEC_TMR3   (*(volatile void *) 0xFFE8) /* Timer channel 3 I bit TMSK1 C3I $E8 */
#define VEC_TMR2   (*(volatile void *) 0xFFEA) /* Timer channel 2 I bit TMSK1 C2I $EA */
#define VEC_TMR1   (*(volatile void *) 0xFFEC) /* Timer channel 1 I bit TMSK1 C1I $EC */
#define VEC_TMR0   (*(volatile void *) 0xFFEE) /* Timer channel 0 I bit TMSK1 C0I $EE */
#define VEC_RTI   (*(volatile void *) 0xFFF0) /* Real­time interrupt I bit RTICTL RTIE $F0 */
#define VEC_IRQ   (*(volatile void *) 0xFFF2) /* IRQ I bit INTCR IRQEN $F2 */
#define VEC_XIRQ   (*(volatile void *) 0xFFF4) /* XIRQ X bit None None --- */
#define VEC_SWI   (*(volatile void *) 0xFFF6) /* SWI None None None --- */
#define VEC_ILLEGAL_OP   (*(volatile void *) 0xFFF8) /* Unimplemented instruction trap None None None --- */
#define VEC_COP_FAIL   (*(volatile void *) 0xFFFA) /* COP failure reset None None COP rate selected --- */
#define VEC_COP_CLK   (*(volatile void *) 0xFFFC) /* COP clock monitor fail reset None COPCTL CME, FCME --- */
#define VEC_RESET   (*(volatile void *) 0xFFFE) /* Reset None None None --- */
#define VEC_TABLE   (*(volatile void *) 0xFFC0)

Enumerations

enum  intrid_t {
  INTRID_CAN_TX = 2, INTRID_CAN_RX = 3, INTRID_CAN_ERR = 4, INTRID_CAN_WAKE = 8,
  INTRID_ATD = 9, INTRID_SCI = 11, INTRID_SPI = 12, INTRID_ACC_INPUT_EDGE = 13,
  INTRID_ACC_OVERFLOW = 14, INTRID_TMR_OVERFLOW = 15, INTRID_TMR7 = 16, INTRID_TMR6 = 17,
  INTRID_TMR5 = 18, INTRID_TMR4 = 19, INTRID_TMR3 = 20, INTRID_TMR2 = 21,
  INTRID_TMR1 = 22, INTRID_TMR0 = 23, INTRID_RTI = 24, INTRID_IRQ = 25,
  INTRID_XIRQ = 26, INTRID_SWI = 27, INTRID_ILLEGAL_OP = 28, INTRID_COP_FAIL = 29,
  INTRID_COP_CLK = 30, INTRID_RESET = 31, INTRID_MAX
}

Functions

void isr_can_tx (void) __attribute__((interrupt))
void isr_can_rx (void) __attribute__((interrupt))
void isr_can_err (void) __attribute__((interrupt))
void isr_can_wake (void) __attribute__((interrupt))
void isr_acc_b_overflow (void) __attribute__((interrupt))
void isr_modcount_underflow (void) __attribute__((interrupt))
void isr_bdlc (void) __attribute__((interrupt))
void isr_atd (void) __attribute__((interrupt))
void isr_sci (void) __attribute__((interrupt))
void isr_spi (void) __attribute__((interrupt))
void isr_acc_input_edge (void) __attribute__((interrupt))
void isr_acc_overflow (void) __attribute__((interrupt))
void isr_tmr_overflow (void) __attribute__((interrupt))
void isr_tmr7 (void) __attribute__((interrupt))
void isr_tmr6 (void) __attribute__((interrupt))
void isr_tmr5 (void) __attribute__((interrupt))
void isr_tmr4 (void) __attribute__((interrupt))
void isr_tmr3 (void) __attribute__((interrupt))
void isr_tmr2 (void) __attribute__((interrupt))
void isr_tmr1 (void) __attribute__((interrupt))
void isr_tmr0 (void) __attribute__((interrupt))
void isr_rti (void) __attribute__((interrupt))
void isr_irq (void) __attribute__((interrupt))
void isr_xirq (void) __attribute__((interrupt))
void isr_swi (void) __attribute__((interrupt))
void isr_illegal_op (void) __attribute__((interrupt))
void isr_cop_fail (void) __attribute__((interrupt))
void isr_cop_clk (void) __attribute__((interrupt))
void isr_reset (void) __attribute__((interrupt))

Define Documentation

#define VEC_ACC_INPUT_EDGE   (*(volatile void *) 0xFFDA) /* Pulse accumulator input edge I bit PACTL PAI $DA */
 

Definition at line 33 of file m68hc12b/vectors.h.

#define VEC_ACC_OVERFLOW   (*(volatile void *) 0xFFDC) /* Pulse accumulator overflow I bit PACTL PAOVI $DC */
 

Definition at line 35 of file m68hc12b/vectors.h.

#define VEC_ATD   (*(volatile void *) 0xFFD2) /* ATD I bit ATDCTL2 ASCIE $D2 */
 

Definition at line 26 of file m68hc12b/vectors.h.

#define VEC_CAN_ERR   (*(volatile void *) 0xFFC8) /* MSCAN errors I bit CRIER - RWRNIE, TWRNIE, RERRIE, TERRIE, BOFFIE, OVRIE $C8 */
 

Definition at line 21 of file m68hc12b/vectors.h.

#define VEC_CAN_RX   (*(volatile void *) 0xFFC6) /* MSCAN receive I bit CRIER RXFIE $C6 */
 

Definition at line 19 of file m68hc12b/vectors.h.

#define VEC_CAN_TX   (*(volatile void *) 0xFFC4) /* MSCAN transmit I bit CTCR TXEIE[2:0] $C4 */
 

Definition at line 17 of file m68hc12b/vectors.h.

#define VEC_CAN_WAKE   (*(volatile void *) 0xFFD0) /* MSCAN wakeup I bit CRIER WUPIE $D0 */
 

Definition at line 24 of file m68hc12b/vectors.h.

#define VEC_COP_CLK   (*(volatile void *) 0xFFFC) /* COP clock monitor fail reset None COPCTL CME, FCME --- */
 

Definition at line 67 of file m68hc12b/vectors.h.

#define VEC_COP_FAIL   (*(volatile void *) 0xFFFA) /* COP failure reset None None COP rate selected --- */
 

Definition at line 65 of file m68hc12b/vectors.h.

#define VEC_ILLEGAL_OP   (*(volatile void *) 0xFFF8) /* Unimplemented instruction trap None None None --- */
 

Definition at line 63 of file m68hc12b/vectors.h.

#define VEC_IRQ   (*(volatile void *) 0xFFF2) /* IRQ I bit INTCR IRQEN $F2 */
 

Definition at line 57 of file m68hc12b/vectors.h.

#define VEC_RESET   (*(volatile void *) 0xFFFE) /* Reset None None None --- */
 

Definition at line 69 of file m68hc12b/vectors.h.

#define VEC_RTI   (*(volatile void *) 0xFFF0) /* Real­time interrupt I bit RTICTL RTIE $F0 */
 

Definition at line 55 of file m68hc12b/vectors.h.

#define VEC_SCI   (*(volatile void *) 0xFFD6) /* SCI 0 I bit SC0CR2 TIE, TCIE, RIE, ILIE $D6 */
 

Definition at line 29 of file m68hc12b/vectors.h.

#define VEC_SPI   (*(volatile void *) 0xFFD8) /* SPI serial transfer complete I bit SP0CR1 SPIE $D8 */
 

Definition at line 31 of file m68hc12b/vectors.h.

#define VEC_SWI   (*(volatile void *) 0xFFF6) /* SWI None None None --- */
 

Definition at line 61 of file m68hc12b/vectors.h.

#define VEC_TABLE   (*(volatile void *) 0xFFC0)
 

For the MC68HC(9)12BC32 device only.

Definition at line 106 of file m68hc12b/vectors.h.

#define VEC_TMR0   (*(volatile void *) 0xFFEE) /* Timer channel 0 I bit TMSK1 C0I $EE */
 

Definition at line 53 of file m68hc12b/vectors.h.

#define VEC_TMR1   (*(volatile void *) 0xFFEC) /* Timer channel 1 I bit TMSK1 C1I $EC */
 

Definition at line 51 of file m68hc12b/vectors.h.

#define VEC_TMR2   (*(volatile void *) 0xFFEA) /* Timer channel 2 I bit TMSK1 C2I $EA */
 

Definition at line 49 of file m68hc12b/vectors.h.

#define VEC_TMR3   (*(volatile void *) 0xFFE8) /* Timer channel 3 I bit TMSK1 C3I $E8 */
 

Definition at line 47 of file m68hc12b/vectors.h.

#define VEC_TMR4   (*(volatile void *) 0xFFE6) /* Timer channel 4 I bit TMSK1 C4I $E6 */
 

Definition at line 45 of file m68hc12b/vectors.h.

#define VEC_TMR5   (*(volatile void *) 0xFFE4) /* Timer channel 5 I bit TMSK1 C5I $E4 */
 

Definition at line 43 of file m68hc12b/vectors.h.

#define VEC_TMR6   (*(volatile void *) 0xFFE2) /* Timer channel 6 I bit TMSK1 C6I $E2 */
 

Definition at line 41 of file m68hc12b/vectors.h.

#define VEC_TMR7   (*(volatile void *) 0xFFE0) /* Timer channel 7 I bit TMSK1 C7I $E0 */
 

Definition at line 39 of file m68hc12b/vectors.h.

#define VEC_TMR_OVERFLOW   (*(volatile void *) 0xFFDE) /* Timer overflow I bit TMSK2 TOI $DE */
 

Definition at line 37 of file m68hc12b/vectors.h.

#define VEC_XIRQ   (*(volatile void *) 0xFFF4) /* XIRQ X bit None None --- */
 

Definition at line 59 of file m68hc12b/vectors.h.

Enumeration Type Documentation

enum intrid_t
 

Enumeration values:
INTRID_CAN_TX 
INTRID_CAN_RX 
INTRID_CAN_ERR 
INTRID_CAN_WAKE 
INTRID_ATD 
INTRID_SCI 
INTRID_SPI 
INTRID_ACC_INPUT_EDGE 
INTRID_ACC_OVERFLOW 
INTRID_TMR_OVERFLOW 
INTRID_TMR7 
INTRID_TMR6 
INTRID_TMR5 
INTRID_TMR4 
INTRID_TMR3 
INTRID_TMR2 
INTRID_TMR1 
INTRID_TMR0 
INTRID_RTI 
INTRID_IRQ 
INTRID_XIRQ 
INTRID_SWI 
INTRID_ILLEGAL_OP 
INTRID_COP_FAIL 
INTRID_COP_CLK 
INTRID_RESET 
INTRID_MAX 

Definition at line 107 of file m68hc12b/vectors.h. 

00117             {   /* Assume 0xFFC0 vector table */
00118         /* 0xFFCE Reserved (implemented) I bit --- --- $CE */
00119         INTRID_ACC_B_OVERFLOW = 5,      /* 0xFFCA */
00120         INTRID_MODCOUNT_UNDERFLOW = 6,  /* 0xFFCC */
00121         /* 0xFFC2 --0xFFC9 Reserved (implemented) I bit --- --- $C2--$C8 */
00122         /* 0xFF80 --0xFFC1 Reserved (not implemented) I bit --- --- $80--$C0 */
00123         INTRID_BDLC =           8,      /* 0xFFD0 */
00124         INTRID_ATD =            9,      /* 0xFFD2 */
00125         /* 0xFFD4 Reserved I bit --- --- $D4 */
00126         INTRID_SCI =            11,     /* 0xFFD6 */
00127         INTRID_SPI =            12,     /* 0xFFD8 */
00128         INTRID_ACC_INPUT_EDGE = 13,     /* 0xFFDA */
00129         INTRID_ACC_OVERFLOW =   14,     /* 0xFFDC */
00130         INTRID_TMR_OVERFLOW =   15,     /* 0xFFDE */
00131         INTRID_TMR7 =           16,     /* 0xFFE0 */
00132         INTRID_TMR6 =           17,     /* 0xFFE2 */
00133         INTRID_TMR5 =           18,     /* 0xFFE4 */
00134         INTRID_TMR4 =           19,     /* 0xFFE6 */
00135         INTRID_TMR3 =           20,     /* 0xFFE8 */
00136         INTRID_TMR2 =           21,     /* 0xFFEA */
00137         INTRID_TMR1 =           22,     /* 0xFFEC */
00138         INTRID_TMR0 =           23,     /* 0xFFEE */

Function Documentation

void isr_acc_b_overflow (  void   ) 
 

void isr_acc_input_edge (  void   ) 
 

void isr_acc_overflow (  void   ) 
 

void isr_atd (  void   ) 
 

void isr_bdlc (  void   ) 
 

void isr_can_err (  void   ) 
 

void isr_can_rx (  void   ) 
 

void isr_can_tx (  void   ) 
 

For the MC68HC(9)12BC32 device only.

void isr_can_wake (  void   ) 
 

void isr_cop_clk (  void   ) 
 

void isr_cop_fail (  void   ) 
 

void isr_illegal_op (  void   ) 
 

void isr_irq (  void   ) 
 

void isr_modcount_underflow (  void   ) 
 

void isr_reset (  void   ) 
 

void isr_rti (  void   ) 
 

void isr_sci (  void   ) 
 

void isr_spi (  void   ) 
 

void isr_swi (  void   ) 
 

void isr_tmr0 (  void   ) 
 

void isr_tmr1 (  void   ) 
 

void isr_tmr2 (  void   ) 
 

void isr_tmr3 (  void   ) 
 

void isr_tmr4 (  void   ) 
 

void isr_tmr5 (  void   ) 
 

void isr_tmr6 (  void   ) 
 

void isr_tmr7 (  void   ) 
 

void isr_tmr_overflow (  void   ) 
 

void isr_xirq (  void   ) 
 

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