BeeOS: vectors.h Source File

00001 
00013 /* #define MC68HC12BC32 */  /* Set vectors for a MC68HC(9)12BC32. */
00014 
00015 #ifndef MC68HC12BC32 /* For all devices except MC68HC(9)12BC32. */
00016 /* 0xFF80 Reserved (implemented) I bit --- --- $80--$C3 */
00017 #define VEC_CAN_TX      (*(volatile void *) 0xFFC4) /* MSCAN transmit I bit CTCR TXEIE[2:0] $C4 */
00018 #define VEC_CAN_RX      (*(volatile void *) 0xFFC6) /* MSCAN receive I bit CRIER RXFIE $C6 */
00019 #define VEC_CAN_ERR     (*(volatile void *) 0xFFC8) /* MSCAN errors I bit CRIER - RWRNIE, TWRNIE, RERRIE, TERRIE, BOFFIE, OVRIE $C8 */
00020 /* 0xFFCA --0xFFCF Reserved (not implemented) I bit --- --- $CA--$CF */
00021 #define VEC_CAN_WAKE    (*(volatile void *) 0xFFD0) /* MSCAN wakeup I bit CRIER WUPIE $D0 */
00022 #define VEC_ATD         (*(volatile void *) 0xFFD2) /* ATD I bit ATDCTL2 ASCIE $D2 */
00023 /* 0xFFD4  Reserved I bit --- --- $D4 */
00024 #define VEC_SCI         (*(volatile void *) 0xFFD6) /* SCI 0 I bit SC0CR2 TIE, TCIE, RIE, ILIE $D6 */
00025 #define VEC_SPI         (*(volatile void *) 0xFFD8) /* SPI serial transfer complete I bit SP0CR1 SPIE $D8 */
00026 #define VEC_ACC_INPUT_EDGE  (*(volatile void *) 0xFFDA) /* Pulse accumulator input edge I bit PACTL PAI $DA */
00027 #define VEC_ACC_OVERFLOW    (*(volatile void *) 0xFFDC) /* Pulse accumulator overflow I bit PACTL PAOVI $DC */
00028 #define VEC_TMR_OVERFLOW    (*(volatile void *) 0xFFDE) /* Timer overflow I bit TMSK2 TOI $DE */
00029 #define VEC_TMR7        (*(volatile void *) 0xFFE0) /* Timer channel 7 I bit TMSK1 C7I $E0 */
00030 #define VEC_TMR6        (*(volatile void *) 0xFFE2) /* Timer channel 6 I bit TMSK1 C6I $E2 */
00031 #define VEC_TMR5        (*(volatile void *) 0xFFE4) /* Timer channel 5 I bit TMSK1 C5I $E4 */
00032 #define VEC_TMR4        (*(volatile void *) 0xFFE6) /* Timer channel 4 I bit TMSK1 C4I $E6 */
00033 #define VEC_TMR3        (*(volatile void *) 0xFFE8) /* Timer channel 3 I bit TMSK1 C3I $E8 */
00034 #define VEC_TMR2        (*(volatile void *) 0xFFEA) /* Timer channel 2 I bit TMSK1 C2I $EA */
00035 #define VEC_TMR1        (*(volatile void *) 0xFFEC) /* Timer channel 1 I bit TMSK1 C1I $EC */
00036 #define VEC_TMR0        (*(volatile void *) 0xFFEE) /* Timer channel 0 I bit TMSK1 C0I $EE */
00037 #define VEC_RTI         (*(volatile void *) 0xFFF0) /* Realtime interrupt I bit RTICTL RTIE $F0 */
00038 #define VEC_IRQ         (*(volatile void *) 0xFFF2) /* IRQ I bit INTCR IRQEN $F2 */
00039 #define VEC_XIRQ        (*(volatile void *) 0xFFF4) /* XIRQ X bit None None --- */
00040 #define VEC_SWI         (*(volatile void *) 0xFFF6) /* SWI None None None --- */
00041 #define VEC_ILLEGAL_OP  (*(volatile void *) 0xFFF8) /* Unimplemented instruction trap None None None --- */
00042 #define VEC_COP_FAIL    (*(volatile void *) 0xFFFA) /* COP failure reset None None COP rate selected --- */
00043 #define VEC_COP_CLK     (*(volatile void *) 0xFFFC) /* COP clock monitor fail reset None COPCTL CME, FCME --- */
00044 #define VEC_RESET       (*(volatile void *) 0xFFFE) /* Reset None None None --- */
00045 #endif
00046 
00047 #ifdef MC68HC12BC32 
00048 #define VEC_ACC_B_OVERFLOW  (*(volatile void *) 0xFFCA) /* Pulse accumulator B overflow I bit PBCTL PBOVI $CA */
00049 #define VEC_MODCOUNT_UNDERFLOW  (*(volatile void *) 0xFFCC) /* Modulus down counter underflow I bit MCCTL MCZI $CC */
00050 /* 0xFFCE Reserved (implemented) I bit --- --- $CE */
00051 /* 0xFFC2 --0xFFC9 Reserved (implemented) I bit --- --- $C2--$C8 */
00052 /* 0xFF80 --0xFFC1 Reserved (not implemented) I bit --- --- $80--$C0 */
00053 #define VEC_BDLC        (*(volatile void *) 0xFFD0) /* BDLC I bit BCR1 IE $D0 */
00054 #define VEC_ATD         (*(volatile void *) 0xFFD2) /* ATD I bit ATDCTL2 ASCIE $D2 */
00055 /* 0xFFD4 Reserved I bit --- --- $D4 */
00056 #define VEC_SCI         (*(volatile void *) 0xFFD6) /* SCI 0 I bit SC0CR2 TIE, TCIE, RIE, ILIE $D6 */
00057 #define VEC_SPI         (*(volatile void *) 0xFFD8) /* SPI serial transfer complete I bit SP0CR1 SPIE $D8 */
00058 #define VEC_ACC_INPUT_EDGE  (*(volatile void *) 0xFFDA) /* Pulse accumulator input edge I bit PACTL PAI $DA */
00059 #define VEC_ACC_OVERFLOW    (*(volatile void *) 0xFFDC) /* Pulse accumulator overflow I bit PACTL PAOVI $DC */
00060 #define VEC_TMR_OVERFLOW    (*(volatile void *) 0xFFDE) /* Timer overflow I bit TMSK2 TOI $DE */
00061 #define VEC_TMR7        (*(volatile void *) 0xFFE0) /* Timer channel 7 I bit TMSK1 C7I $E0 */
00062 #define VEC_TMR6        (*(volatile void *) 0xFFE2) /* Timer channel 6 I bit TMSK1 C6I $E2 */
00063 #define VEC_TMR5        (*(volatile void *) 0xFFE4) /* Timer channel 5 I bit TMSK1 C5I $E4 */
00064 #define VEC_TMR4        (*(volatile void *) 0xFFE6) /* Timer channel 4 I bit TMSK1 C4I $E6 */
00065 #define VEC_TMR3        (*(volatile void *) 0xFFE8) /* Timer channel 3 I bit TMSK1 C3I $E8 */
00066 #define VEC_TMR2        (*(volatile void *) 0xFFEA) /* Timer channel 2 I bit TMSK1 C2I $EA */
00067 #define VEC_TMR1        (*(volatile void *) 0xFFEC) /* Timer channel 1 I bit TMSK1 C1I $EC */
00068 #define VEC_TMR0        (*(volatile void *) 0xFFEE) /* Timer channel 0 I bit TMSK1 C0I $EE */
00069 #define VEC_RTI         (*(volatile void *) 0xFFF0) /* Realtime interrupt I bit RTICTL RTIE $F0 */
00070 #define VEC_IRQ         (*(volatile void *) 0xFFF2) /* IRQ I bit INTCR IRQEN $F2 */
00071 #define VEC_XIRQ        (*(volatile void *) 0xFFF4) /* XIRQ X bit None None --- */
00072 #define VEC_SWI         (*(volatile void *) 0xFFF6) /* SWI None None None --- */
00073 #define VEC_ILLEGAL_OP  (*(volatile void *) 0xFFF8) /* Unimplemented instruction trap None None None --- */
00074 #define VEC_COP_FAIL    (*(volatile void *) 0xFFFA) /* COP failure reset None None COP rate selected --- */
00075 #define VEC_COP_CLK     (*(volatile void *) 0xFFFC) /* COP clock monitor fail reset None COPCTL CME, FCME --- */
00076 #define VEC_RESET       (*(volatile void *) 0xFFFE) /* Reset None None None --- */
00077 #endif
00078 
00079 #ifndef MC68HC12BC32 /* For all devices except MC68HC(9)12BC32. */
00080 #   define VEC_TABLE        (*(volatile void *) 0xFFC0)
00081     typedef enum {  /* Assume 0xFFC0 vector table */
00082         /* 0xFF80 Reserved (implemented) I bit --- --- $80--$C3 */
00083         INTRID_CAN_TX =     2,      /* 0xFFC4 */
00084         INTRID_CAN_RX =     3,      /* 0xFFC6 */
00085         INTRID_CAN_ERR =    4,      /* 0xFFC8 */
00086         /* 0xFFCA --0xFFCF Reserved (not implemented) I bit --- --- $CA--$CF */
00087         INTRID_CAN_WAKE =   8,  /* 0xFFD0 */
00088         INTRID_ATD =        9,      /* 0xFFD2 */
00089         /* 0xFFD4 Reserved I bit --- --- $D4 */
00090         INTRID_SCI =        11,     /* 0xFFD6 */
00091         INTRID_SPI =        12,     /* 0xFFD8 */
00092         INTRID_ACC_INPUT_EDGE = 13, /* 0xFFDA */
00093         INTRID_ACC_OVERFLOW = 14,   /* 0xFFDC */
00094         INTRID_TMR_OVERFLOW = 15,   /* 0xFFDE */
00095         INTRID_TMR7 =       16,     /* 0xFFE0 */
00096         INTRID_TMR6 =       17,     /* 0xFFE2 */
00097         INTRID_TMR5 =       18,     /* 0xFFE4 */
00098         INTRID_TMR4 =       19,     /* 0xFFE6 */
00099         INTRID_TMR3 =       20,     /* 0xFFE8 */
00100         INTRID_TMR2 =       21,     /* 0xFFEA */
00101         INTRID_TMR1 =       22,     /* 0xFFEC */
00102         INTRID_TMR0 =       23,     /* 0xFFEE */
00103         INTRID_RTI =        24,     /* 0xFFF0 */
00104         INTRID_IRQ =        25,     /* 0xFFF2 */
00105         INTRID_XIRQ =       26,     /* 0xFFF4 */
00106         INTRID_SWI =        27,     /* 0xFFF6 */
00107         INTRID_ILLEGAL_OP = 28,     /* 0xFFF8 */
00108         INTRID_COP_FAIL =   29,     /* 0xFFFA */
00109         INTRID_COP_CLK =    30,     /* 0xFFFC */
00110         INTRID_RESET =      31,     /* 0xFFFE */
00111         INTRID_MAX
00112     } intrid_t;
00113 #endif
00114 
00115 #ifdef MC68HC12BC32 
00116 #   define VEC_TABLE        (*(volatile void *) 0xFFC0)
00117     typedef {   /* Assume 0xFFC0 vector table */
00118         /* 0xFFCE Reserved (implemented) I bit --- --- $CE */
00119         INTRID_ACC_B_OVERFLOW = 5,      /* 0xFFCA */
00120         INTRID_MODCOUNT_UNDERFLOW = 6,  /* 0xFFCC */
00121         /* 0xFFC2 --0xFFC9 Reserved (implemented) I bit --- --- $C2--$C8 */
00122         /* 0xFF80 --0xFFC1 Reserved (not implemented) I bit --- --- $80--$C0 */
00123         INTRID_BDLC =           8,      /* 0xFFD0 */
00124         INTRID_ATD =            9,      /* 0xFFD2 */
00125         /* 0xFFD4 Reserved I bit --- --- $D4 */
00126         INTRID_SCI =            11,     /* 0xFFD6 */
00127         INTRID_SPI =            12,     /* 0xFFD8 */
00128         INTRID_ACC_INPUT_EDGE = 13,     /* 0xFFDA */
00129         INTRID_ACC_OVERFLOW =   14,     /* 0xFFDC */
00130         INTRID_TMR_OVERFLOW =   15,     /* 0xFFDE */
00131         INTRID_TMR7 =           16,     /* 0xFFE0 */
00132         INTRID_TMR6 =           17,     /* 0xFFE2 */
00133         INTRID_TMR5 =           18,     /* 0xFFE4 */
00134         INTRID_TMR4 =           19,     /* 0xFFE6 */
00135         INTRID_TMR3 =           20,     /* 0xFFE8 */
00136         INTRID_TMR2 =           21,     /* 0xFFEA */
00137         INTRID_TMR1 =           22,     /* 0xFFEC */
00138         INTRID_TMR0 =           23,     /* 0xFFEE */
00139         INTRID_RTI =            24,     /* 0xFFF0 */
00140         INTRID_IRQ =            25,     /* 0xFFF2 */
00141         INTRID_XIRQ =           26,     /* 0xFFF4 */
00142         INTRID_SWI =            27,     /* 0xFFF6 */
00143         INTRID_ILLEGAL_OP =     28,     /* 0xFFF8 */
00144         INTRID_COP_FAIL =       29,     /* 0xFFFA */
00145         INTRID_COP_CLK =        30,     /* 0xFFFC */
00146         INTRID_RESET =          31,     /* 0xFFFE */
00147         INTRID_MAX
00148     } intrid_t;
00149 #endif
00150 
00151 void isr_can_tx             (void) __attribute__ ((interrupt)); /* 0xffc4 */
00152 void isr_can_rx             (void) __attribute__ ((interrupt)); /* 0xffc6 */
00153 void isr_can_err            (void) __attribute__ ((interrupt)); /* 0xffc8 */
00154 void isr_can_wake           (void) __attribute__ ((interrupt)); /* 0xffd0 */
00155 void isr_acc_b_overflow     (void) __attribute__ ((interrupt)); /* 0xFFCA */
00156 void isr_modcount_underflow (void) __attribute__ ((interrupt)); /* 0xFFCC */
00157 void isr_bdlc               (void) __attribute__ ((interrupt)); /* 0xFFD0 */
00158 void isr_atd                (void) __attribute__ ((interrupt)); /* 0xFFD2 */
00159 void isr_sci                (void) __attribute__ ((interrupt)); /* 0xFFD6 */
00160 void isr_spi                (void) __attribute__ ((interrupt)); /* 0xFFD8 */
00161 void isr_acc_input_edge     (void) __attribute__ ((interrupt)); /* 0xFFDA */
00162 void isr_acc_overflow       (void) __attribute__ ((interrupt)); /* 0xFFDC */
00163 void isr_tmr_overflow       (void) __attribute__ ((interrupt)); /* 0xFFDE */
00164 void isr_tmr7               (void) __attribute__ ((interrupt)); /* 0xFFE0 */
00165 void isr_tmr6               (void) __attribute__ ((interrupt)); /* 0xFFE2 */
00166 void isr_tmr5               (void) __attribute__ ((interrupt)); /* 0xFFE4 */
00167 void isr_tmr4               (void) __attribute__ ((interrupt)); /* 0xFFE6 */
00168 void isr_tmr3               (void) __attribute__ ((interrupt)); /* 0xFFE8 */
00169 void isr_tmr2               (void) __attribute__ ((interrupt)); /* 0xFFEA */
00170 void isr_tmr1               (void) __attribute__ ((interrupt)); /* 0xFFEC */
00171 void isr_tmr0               (void) __attribute__ ((interrupt)); /* 0xFFEE */
00172 void isr_rti                (void) __attribute__ ((interrupt)); /* 0xFFF0 */
00173 void isr_irq                (void) __attribute__ ((interrupt)); /* 0xFFF2 */
00174 void isr_xirq               (void) __attribute__ ((interrupt)); /* 0xFFF4 */
00175 void isr_swi                (void) __attribute__ ((interrupt)); /* 0xFFF6 */
00176 void isr_illegal_op         (void) __attribute__ ((interrupt)); /* 0xFFF8 */
00177 void isr_cop_fail           (void) __attribute__ ((interrupt)); /* 0xFFFA */
00178 void isr_cop_clk            (void) __attribute__ ((interrupt)); /* 0xFFFC */
00179 void isr_reset              (void) __attribute__ ((interrupt)); /* 0xFFFE */