00001 00009 /* CRG.H CONFIG START */ 00010 /* CRG.H CONFIG END */ 00011 00012 /* CRGFLG (CRG Flags Register, from pp19) */ 00013 #define CRG_RTIF 0x80 /* Real Time Interrupt Flag */ 00014 #define CRG_PORF 0x40 /* Power on Reset Flag */ 00015 #define CRG_LOCKIF 0x10 /* PLL Lock Interrupt Flag */ 00016 #define CRG_LOCK 0x08 /* Lock Status Bit */ 00017 #define CRG_TRACK 0x04 /* Track Status Bit */ 00018 #define CRG_SCMIF 0x02 /* Self Clock Mode Interrupt Flag */ 00019 #define CRG_SCM 0x01 /* Self Clock Mode Status Bit */ 00020 /* CRGINT (CRG Interrupt Enable Register, from pp20) */ 00021 #define CRG_RTIE 0x80 /* Real Time Interrupt Enable Bit */ 00022 #define CRG_LOCKIE 0x10 /* Lock Interrupt Enable Bit */ 00023 #define CRG_SCMIE 0x02 /* Self Clock Mode Interrupt Enable Bit */ 00024 /* CLKSEL (CRG Clock Select Register, from pp21) */ 00025 #define CRG_PLLSEL 0x80 /* PLL Select Bit */ 00026 #define CRG_PSTP 0x40 /* Pseudo Stop Bit */ 00027 #define CRG_SYSWAI 0x20 /* System clocks stop in Wait Mode Bit */ 00028 #define CRG_ROAWAI 0x10 /* Reduced Oscillator Amplitude in Wait Mode Bit */ 00029 #define CRG_PLLWAI 0x08 /* PLL stops in Wait Mode Bit */ 00030 #define CRG_CWAWAI 0x04 /* Core stops in Wait Mode Bit */ 00031 #define CRG_RTIWAI 0x02 /* RTI stops in Wait Mode Bit */ 00032 #define CRG_COPWAI 0x01 /* COP stops in Wait Mode Bit */ 00033 /* PLLCTL (CRG PLL Control Register PLLCTL, from pp23) */ 00034 #define CRG_CME 0x80 /* Clock Monitor Enable Bit */ 00035 #define CRG_PLLON 0x40 /* Phase Lock Loop On Bit */ 00036 #define CRG_AUTO 0x20 /* Automatic Bandwidth Control Bit */ 00037 #define CRG_ACQ 0x10 /* Acquisition Bit */ 00038 #define CRG_PRE 0x04 /* RTI Enable during Pseudo Stop Bit */ 00039 #define CRG_PCE 0x02 /* COP Enable during Pseudo Stop Bit */ 00040 #define CRG_SCME 0x00 /* Self Clock Mode Enable Bit */ 00041 /* COPCTL (CRG COP Control Register, from pp26) */ 00042 #define CRG_WCOP 0x80 /* Window COP Mode Bit */ 00043 #define CRG_RSBCK 0x40 /* COP and RTI stop in Active BDM mode Bit */ 00044 #define CRG_CR2 0x04 /* CR[2:0] COP Watchdog Timer Rate select */ 00045 #define CRG_CR1 0x02 /* CR[2:0] COP Watchdog Timer Rate select */ 00046 #define CRG_CR0 0x01 /* CR[2:0] COP Watchdog Timer Rate select */ 00047 00048 /* <tt> 00049 * CRGFLG (CRG Flags Register, from pp19) 00050 * bit name normal descr. 00051 * ------------------------------- 00052 * 7 RTIF Real Time Interrupt Flag RTIF set to 1 at end of the RTI 00053 period. This flag can only be cleared by writing a 1. 00054 If enabled (RTIE=1), RTIF causes an interrupt request. 00055 * 6 PORF Power on Reset Flag PORF set to 1 when a power on reset occurs. 00056 This flag can only be cleared by writing a 1. 00057 * 4 LOCKIF PLL Lock Interrupt Flag LOCKIF set to 1 when LOCK status bit 00058 changes. This flag can only be cleared by writing a 1. 00059 If enabled (LOCKIE=1), LOCKIF causes an interrupt request. 00060 * 3 LOCK Lock Status Bit LOCK reflects the current state of PLL lock 00061 condition. This bit is cleared in Self Clock Mode. Writes have 00062 no effect. 1 = PLL VCO is within the desired tolerance of the 00063 target frequency. 00064 * 2 TRACK Track Status Bit TRACK reflects the current state of PLL 00065 track condition. This bit is cleared in Self Clock Mode. 00066 Writes have no effect. 00067 * 1 SCMIF Self Clock Mode Interrupt Flag SCMIF set to 1 when SCM status 00068 bit changes. This flag can only be cleared by writing a 1. 00069 If enabled (SCMIE=1), SCMIF causes an interrupt request. 00070 * 0 SCM Self Clock Mode Status Bit SCM reflects the current clocking 00071 mode. Writes have no effect. 1 = MCU is operating in Self Clock 00072 Mode with OSCCLK in an unknown state. All clocks are derived from 00073 PLLCLK running at its minimum frequency fSCM. 00074 00075 * </tt> 00076 */ 00077 00078 /* <tt> 00079 * CRGINT (CRG Interrupt Enable Register, from pp20) 00080 * bit name normal descr. 00081 * ------------------------------- 00082 * 7 RTIE Real Time Interrupt Enable Bit. 1 = Interrupt will be 00083 requested whenever RTIF is set. 00084 * 4 LOCKIE Lock Interrupt Enable Bit 1 = Interrupt will be requested 00085 whenever LOCKIF is set. 00086 * 1 SCMIE Self Clock Mode Interrupt Enable Bit 1 = Interrupt will be 00087 requested whenever SCMIF is set. 00088 * 00089 * </tt> 00090 */ 00091 00092 /* <tt> 00093 * CLKSEL (CRG Clock Select Register, from pp21) 00094 * bit name normal descr. 00095 * ------------------------------- 00096 * 7 PLLSEL PLL Select Bit 00097 * Write anytime except when LOCK=0 and AUTO=1, or TRACK=0 and 00098 AUTO=0. PLLSEL bit is cleared when the MCU enters Self Clock Mode, 00099 Stop Mode or Wait Mode with PLLWAI bit set. 00100 1 = System clocks are derived from PLLCLK. 00101 0 = System clocks are derived from OSCCLK. 00102 * 6 PSTP Pseudo Stop Bit Write: anytime This bit controls the 00103 functionality of the oscillator during Stop Mode. 00104 1 = Oscillator continues to run in Stop Mode (Pseudo Stop). 00105 The oscillator amplitude is reduced. 00106 0 = Oscillator is disabled in Stop Mode. 00107 NOTE: Pseudo-STOP allows for faster STOP recovery and reduces 00108 the mechanical stress and aging of the resonator in case of 00109 frequent STOP conditions at the expense of a slightly increased 00110 power consumption. Lower oscillator amplitude exhibits lower 00111 power consumption but could have adverse effects during any 00112 Electro-Magnetic Susceptibility (EMS) tests. 00113 * 5 SYSWAI System clocks stop in Wait Mode Bit Write: anytime 00114 1 = In Wait Mode the system clocks stop. 00115 0 = In Wait Mode the system clocks continue to run. 00116 NOTE: RTI and COP are not affected by SYSWAI bit. 00117 * 4 ROAWAI Reduced Oscillator Amplitude in Wait Mode Bit. Write: anytime 00118 1 = Reduced oscillator amplitude in Wait Mode. 00119 0 = Normal oscillator amplitude in Wait Mode. 00120 NOTE: Lower oscillator amplitude exhibits lower power consumption 00121 but could have adverse effects during any Electro-Magnetic 00122 Susceptibility (EMS) tests. 00123 * 3 PLLWAI PLL stops in Wait Mode Bit Write: anytime If PLLWAI is set, 00124 the CRG will clear the PLLSEL bit before entering Wait Mode. 00125 The PLLON bit remains set during Wait Mode but the PLL is 00126 powered down. Upon exiting Wait Mode, the PLLSEL bit has to be 00127 set manually in case PLL clock is required. While the PLLWAI bit 00128 is set the AUTO bit is set to 1 in order to allow the PLL 00129 to automatically lock on the selected target frequency after 00130 exiting Wait Mode. 1 = PLL stops in Wait Mode. 00131 0 = PLL keeps running in Wait Mode. 00132 * 2 CWAI Core stops in Wait Mode Bit Write: anytime 00133 1 = Core clock stops in Wait Mode. 00134 0 = Core clock keeps running in Wait Mode. 00135 * 1 RTIWAI RTI stops in Wait Mode Bit Write: anytime 00136 1 = RTI stops and initializes the RTI dividers whenever the part 00137 goes into Wait Mode. 00138 0 = RTI keeps running in Wait Mode. 00139 * 0 COPWAI COP stops in Wait Mode Bit Normal modes: Write once Special 00140 modes: Write anytime 00141 1 = COP stops and initializes the COP dividers whenever the 00142 part goes into Wait Mode. 00143 0 = COP keeps running in Wait Mode. 00144 * </tt> 00145 */ 00146 00147 /* <tt> 00148 * PLLCTL (CRG PLL Control Register PLLCTL, from pp23) 00149 * bit name normal descr. 00150 * ------------------------------- 00151 * 7 CME Clock Monitor Enable Bit CME enables the clock monitor. 00152 Write anytime except when SCM = 1. 00153 1 = Clock monitor is enabled. Slow or stopped clocks will cause 00154 a clock monitor reset sequence or Self Clock Mode. 00155 0 = Clock monitor is disabled. NOTE: Operating with CME=0 00156 will not detect any loss of clock. In case of poor clock 00157 quality this could cause unpredictable operation of the MCU! 00158 In Stop Mode (PSTP=0) the clock monitor is disabled independently 00159 of the CME bit setting and any loss of clock will not be detected. 00160 * 6 PLLON Phase Lock Loop On Bit PLLON turns on the PLL circuitry. 00161 In Self Clock Mode, the PLL is turned on, but the PLLON bit 00162 reads the last latched value. Write anytime except when PLLSEL = 1. 00163 1 = PLL is turned on. If AUTO bit is set, the PLL will lock 00164 automatically. 00165 0 = PLL is turned off. 00166 * 5 AUTO Automatic Bandwidth Control Bit AUTO selects either the high 00167 bandwidth (acquisition) mode or the low bandwidth (tracking) 00168 mode depending on how close to the desired frequency the VCO 00169 is running. Write anytime except when PLLWAI=1, because PLLWAI 00170 sets the AUTO bit to 1. 00171 1 = Automatic Mode Control is enabled and ACQ bit has no effect. 00172 0 = Automatic Mode Control is disabled and the PLL is under software 00173 control, using ACQ bit. 00174 * 4 ACQ Acquisition Bit Write anytime. If AUTO=1 this bit has no effect. 00175 1 = High bandwidth filter is selected. 00176 0 = Low bandwidth filter is selected. 00177 * 2 PRE RTI Enable during Pseudo Stop Bit PRE enables the RTI during 00178 Pseudo Stop Mode. 00179 1 = RTI continues running during Pseudo Stop Mode. 00180 0 = RTI stops running during Pseudo Stop Mode. NOTE: If the PRE 00181 bit is cleared the RTI dividers will go static while Pseudo-Stop 00182 Mode is active. The RTI dividers will not initialize like 00183 in Wait Mode with RTIWAI bit set. 00184 * 1 PCE COP Enable during Pseudo Stop Bit PCE enables the COP during 00185 Pseudo Stop Mode. 00186 1 = COP continues running during Pseudo Stop Mode 00187 0 = COP stops running during Pseudo Stop Mode NOTE: If the PCE 00188 bit is cleared the COP dividers will go static while Pseudo-Stop 00189 Mode is active. The COP dividers will not initialize like 00190 in Wait Mode with COPWAI bit set. 00191 * 0 SCME Self Clock Mode Enable Bit Normal modes: Write once Special 00192 modes: Write anytime 00193 0 = Detection of crystal clock failure causes clock monitor 00194 reset (see 5.2.1 Clock Monitor Reset). 00195 1 = Detection of crystal clock failure forces the MCU in Self 00196 Clock Mode (see 4.3.2 Self Clock Mode). 00197 * </tt> 00198 */ 00199 00200 /* <tt> 00201 * RTICTL (CRG RTI Control Register, from pp24) 00202 * NOTE: A write to this register initializes the RTI counter. 00203 * bit name normal descr. 00204 * ------------------------------- 00205 * RTR[6:4] Real Time Interrupt Prescale Rate Select Bits 00206 These bits select the prescale rate for the RTI. See Table 32. 00207 * RTR[3:0] Real Time Interrupt Modulus Counter Select Bits 00208 These bits select the modulus counter target value to 00209 provide additional granularity.Table 32 shows 00210 all possible divide values selectable by the RTICTL register. 00211 The source clock for the RTI is OSCCLK. Address Offset: $_07 00212 Table 3-2 - Frequency Divide Rate: 00213 RTR[6:4]: 00214 000 001 010 011 100 101 110 111 00215 RTR[3:0]: (OFF) (2^10 ) (2^11) (2^12) (2^13) (2^14) (2^15) (2^16) 00216 0000 (÷1) OFF* 2^10 2^11 2^12 2^13 2^14 2^15 2^16 00217 0001 (÷2) OFF* 2x2^10 2x2^11 2x2^12 2x2^13 2x2^14 2x2^15 2x2^16 00218 0010 (÷3) OFF* 3x2^10 3x2^11 3x2^12 3x2^13 3x2^14 3x2^15 3x2^16 00219 0011 (÷4) OFF* 4x2^10 4x2^11 4x2^12 4x2^13 4x2^14 4x2^15 4x2^16 00220 0100 (÷5) OFF* 5x2^10 5x2^11 5x2^12 5x2^13 5x2^14 5x2^15 5x2^16 00221 0101 (÷6) OFF* 6x2^10 6x2^11 6x2^12 6x2^13 6x2^14 6x2^15 6x2^16 00222 0110 (÷7) OFF* 7x2^10 7x2^11 7x2^12 7x2^13 7x2^14 7x2^15 7x2^16 00223 0111 (÷8) OFF* 8x2^10 8x2^11 8x2^12 8x2^13 8x2^14 8x2^15 8x2^16 00224 1000 (÷9) OFF* 9x2^10 9x2^11 9x2^12 9x2^13 9x2^14 9x2^15 9x2^16 00225 1001 (÷10) OFF* 10x2^10 10x2^11 10x2^12 10x2^13 10x2^14 10x2^15 10x2^16 00226 1010 (÷11) OFF* 11x2^10 11x2^11 11x2^12 11x2^13 11x2^14 11x2^15 11x2^16 00227 1011 (÷12) OFF* 12x2^10 12x2^11 12x2^12 12x2^13 12x2^14 12x2^15 12x2^16 00228 1100 (÷13) OFF* 13x2^10 13x2^11 13x2^12 13x2^13 13x2^14 13x2^15 13x2^16 00229 1101 (÷14) OFF* 14x2^10 14x2^11 14x2^12 14x2^13 14x2^14 14x2^15 14x2^16 00230 1110 (÷15) OFF* 15x2^10 15x2^11 15x2^12 15x2^13 15x2^14 15x2^15 15x2^16 00231 1111 (÷16) OFF* 16x2^10 16x2^11 16x2^12 16x2^13 16x2^14 16x2^15 16x2^16 00232 * </tt> 00233 */ 00234 00235 /* <tt> 00236 * COPCTL (CRG COP Control Register, from pp26) 00237 * bit name normal descr. 00238 * ------------------------------- 00239 * 7 WCOP Window COP Mode Bit When set, a write to the ARMCOP register 00240 must occur in the last 25% of the selected period. A write 00241 during the first 75% of the selected period will reset the part. 00242 As long as all writes occur during this window, $55 can be 00243 written as often as desired. Once $AA is written after the $55, 00244 the time-out logic restarts and the user must wait until the next 00245 window before writing to ARMCOP. Table 3-3 shows the exact 00246 duration of this window for the seven available COP rates. 00247 1 = Window COP operation 00248 0 = Normal COP operation 00249 * 6 RSBCK COP and RTI stop in Active BDM mode Bit 00250 1 = Stops the COP and RTI counters whenever the part is in 00251 Active BDM mode. 00252 0 = Allows the COP and RTI to keep running in Active BDM mode. 00253 * [2:0] CR[2:0] COP Watchdog Timer Rate select These bits select the COP 00254 time-out rate (see Table 3-3). The COP time-out period is 00255 OSCCLK period divided by CR[2:0] value. Writing a nonzero value 00256 to CR[2:0] enables the COP counter and starts the time-out 00257 period. A COP counter time-out causes a system reset. This can 00258 be avoided by periodically (before time-out) reinitializing the 00259 COP counter via the ARMCOP register. Table 3-3 COP Watchdog 00260 Rates1 NOTES: 1. OSCCLK cycles are referenced from the previous 00261 COP time-out reset (writing $55/$AA to the ARMCOP register) 00262 CR2 CR1 CR0 OSCCLK cycles to time-out 00263 0 0 0 COP disabled 00264 0 0 1 2^14 00265 0 1 0 2^16 00266 0 1 1 2^18 00267 1 0 0 2^20 00268 1 0 1 2^22 00269 1 1 0 2^23 00270 1 1 1 2^24 00271 * </tt> 00272 */ 00273 00274 #define OFF_SYNR 0x00 /* CRG Synthesizer Register R/W */ 00275 #define OFF_REFDV 0x01 /* CRG Reference Divider Register R/W */ 00276 #define OFF_CTFLG 0x02 /* CRG Test Flags Register 1 */ 00277 /* NOTES: 1. CTFLG is intended for factory test purposes only. R/W */ 00278 #define OFF_CRGFLG 0x03 /* CRG Flags Register R/W */ 00279 #define OFF_CRGINT 0x04 /* CRG Interrupt Enable Register R/W */ 00280 #define OFF_CLKSEL 0x05 /* CRG Clock Select Register R/W */ 00281 #define OFF_PLLCTL 0x06 /* CRG PLL Control Register R/W */ 00282 #define OFF_RTICTL 0x07 /* CRG RTI Control Register R/W */ 00283 #define OFF_COPCTL 0x08 /* CRG COP Control Register R/W */ 00284 #define OFF_FORBYP 0x09 /* CRG Force and Bypass Test Register 2 */ 00285 /* 2. FORBYP is intended for factory test purposes only. R/W */ 00286 #define OFF_CTCTL 0x0A /* CRG Test Control Register 3 */ 00287 /* 3. CTCTL is intended for factory test purposes only. R/W */ 00288 #define OFF_ARMCOP 0x0B /* CRG COP Arm/Timer Reset R/W */
1.3.6-20040222