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Defines |
| #define | CRG_RTIF 0x80 /* Real Time Interrupt Flag */ |
| #define | CRG_PORF 0x40 /* Power on Reset Flag */ |
| #define | CRG_LOCKIF 0x10 /* PLL Lock Interrupt Flag */ |
| #define | CRG_LOCK 0x08 /* Lock Status Bit */ |
| #define | CRG_TRACK 0x04 /* Track Status Bit */ |
| #define | CRG_SCMIF 0x02 /* Self Clock Mode Interrupt Flag */ |
| #define | CRG_SCM 0x01 /* Self Clock Mode Status Bit */ |
| #define | CRG_RTIE 0x80 /* Real Time Interrupt Enable Bit */ |
| #define | CRG_LOCKIE 0x10 /* Lock Interrupt Enable Bit */ |
| #define | CRG_SCMIE 0x02 /* Self Clock Mode Interrupt Enable Bit */ |
| #define | CRG_PLLSEL 0x80 /* PLL Select Bit */ |
| #define | CRG_PSTP 0x40 /* Pseudo Stop Bit */ |
| #define | CRG_SYSWAI 0x20 /* System clocks stop in Wait Mode Bit */ |
| #define | CRG_ROAWAI 0x10 /* Reduced Oscillator Amplitude in Wait Mode Bit */ |
| #define | CRG_PLLWAI 0x08 /* PLL stops in Wait Mode Bit */ |
| #define | CRG_CWAWAI 0x04 /* Core stops in Wait Mode Bit */ |
| #define | CRG_RTIWAI 0x02 /* RTI stops in Wait Mode Bit */ |
| #define | CRG_COPWAI 0x01 /* COP stops in Wait Mode Bit */ |
| #define | CRG_CME 0x80 /* Clock Monitor Enable Bit */ |
| #define | CRG_PLLON 0x40 /* Phase Lock Loop On Bit */ |
| #define | CRG_AUTO 0x20 /* Automatic Bandwidth Control Bit */ |
| #define | CRG_ACQ 0x10 /* Acquisition Bit */ |
| #define | CRG_PRE 0x04 /* RTI Enable during Pseudo Stop Bit */ |
| #define | CRG_PCE 0x02 /* COP Enable during Pseudo Stop Bit */ |
| #define | CRG_SCME 0x00 /* Self Clock Mode Enable Bit */ |
| #define | CRG_WCOP 0x80 /* Window COP Mode Bit */ |
| #define | CRG_RSBCK 0x40 /* COP and RTI stop in Active BDM mode Bit */ |
| #define | CRG_CR2 0x04 /* CR[2:0] COP Watchdog Timer Rate select */ |
| #define | CRG_CR1 0x02 /* CR[2:0] COP Watchdog Timer Rate select */ |
| #define | CRG_CR0 0x01 /* CR[2:0] COP Watchdog Timer Rate select */ |
| #define | OFF_SYNR 0x00 /* CRG Synthesizer Register R/W */ |
| #define | OFF_REFDV 0x01 /* CRG Reference Divider Register R/W */ |
| #define | OFF_CTFLG 0x02 /* CRG Test Flags Register 1 */ |
| #define | OFF_CRGFLG 0x03 /* CRG Flags Register R/W */ |
| #define | OFF_CRGINT 0x04 /* CRG Interrupt Enable Register R/W */ |
| #define | OFF_CLKSEL 0x05 /* CRG Clock Select Register R/W */ |
| #define | OFF_PLLCTL 0x06 /* CRG PLL Control Register R/W */ |
| #define | OFF_RTICTL 0x07 /* CRG RTI Control Register R/W */ |
| #define | OFF_COPCTL 0x08 /* CRG COP Control Register R/W */ |
| #define | OFF_FORBYP 0x09 /* CRG Force and Bypass Test Register 2 */ |
| #define | OFF_CTCTL 0x0A /* CRG Test Control Register 3 */ |
| #define | OFF_ARMCOP 0x0B /* CRG COP Arm/Timer Reset R/W */ |
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