00001 00009 __inline__ void ect_init(void); 00010 00011 /* ECT.H CONFIG START */ 00012 #define TCNT_CLK 64 /* TCNT rate is 64us, check ect_init. */ 00013 #define MSEC2TCNT(ms) ((ms*1000) / TCNT_CLK) 00014 /* ECT.H CONFIG END */ 00015 00016 /* TSCR1 (Timer System Controler Register 1, from pp22) */ 00017 #define ECT_TEN 0x80 /* Timer Enable */ 00018 #define ECT_TSWAI 0x40 /* Timer Module Stops While in Wait */ 00019 #define ECT_TSFRZ 0x20 /* Timer and Modulus Counter Stop While in Freeze Mode */ 00020 #define ECT_TFFCA 0x10 /* Timer Fast Flag Clear All */ 00021 /* TSCR2 (Timer System Controler Register 2, from pp25) */ 00022 #define ECT_TOI 0x80 /* Timer Overflow Interrupt Enable (intr on TOF flag set) */ 00023 #define ECT_TCRE 0x08 /* Timer Counter Reset Enable */ 00024 #define ECT_PR2 0x04 /* PR2, PR1, PR0 Timer Prescaler Select */ 00025 #define ECT_PR1 0x02 /* PR2, PR1, PR0 Timer Prescaler Select */ 00026 #define ECT_PR0 0x01 /* PR2, PR1, PR0 Timer Prescaler Select */ 00027 /* TFLG2 (Main Timer Interrupt Flag 2, from pp27) */ 00028 #define ECT_TOF 0x80 /* Timer Overflow Flag */ 00029 /* PACTL (16 bit Pulse Accumulator A, from pp29) */ 00030 #define ECT_PAEN 0x40 /* Pulse Accumulator A System Enable */ 00031 #define ECT_PAMOD 0x20 /* Pulse Accumulator Mode */ 00032 #define ECT_PEDGE 0x10 /* Pulse Accumulator Edge Control */ 00033 #define ECT_CLK1 0X08 /* CLK1 CLK0 Clock Source */ 00034 #define ECT_CLK2 0x04 /* CLK1 CLK0 Clock Source */ 00035 #define ECT_PAOVI 0x02 /* Pulse Accumulator A Overflow Interrupt enable */ 00036 #define ECT_PAI 0x01 /* Pulse Accumulator Input Interrupt enable */ 00037 /* PAFLG (Pulse Accumulator A Flag Register, from pp31) */ 00038 #define ECT_PAOVF 0x02 /* Pulse Accumulator A Overflow Flag */ 00039 #define ECT_PAIF 0x01 /* Pulse Accumulator Input edge Flag */ 00040 /* MCCTL (16-Bit Modulus Down-Counter Control Register, from pp33) */ 00041 #define ECT_MCCTL 0x80 /* Modulus Counter Underflow Interrupt Enable */ 00042 #define ECT_MODMC 0x40 /* Modulus Mode Enable */ 00043 #define ECT_RDMCL 0x20 /* Read Modulus Down-Counter Load */ 00044 #define ECT_ICLAT 0x10 /* Input Capture Force Latch Action */ 00045 #define ECT_FLMC 0x08 /* Force Load Register into the Modulus Counter Count Register */ 00046 #define ECT_MCEN 0x04 /* Modulus Down-Counter Enable */ 00047 #define ECT_MCPR1 0x02 /* MCPR1, MCPR0 Modulus Counter Prescaler select */ 00048 #define ECT_MCPR0 0x01 /* MCPR1, MCPR0 Modulus Counter Prescaler select */ 00049 /* MCFLG (16-Bit Modulus Down-Counter FLAG Register, from pp35) */ 00050 #define ECT_MCZF 0x80 /* Modulus Counter Underflow Flag */ 00051 /* PBCTL (16-Bit Pulse Accumulator B Control Register, from pp39) */ 00052 #define ECT_PBEN 0x40 /* Pulse Accumulator B System Enable */ 00053 #define ECT_PBOVI 0x02 /* Pulse Accumulator B Overflow Interrupt enable */ 00054 /* PBFLG (Pulse Accumulator B Flag Register, from pp40) */ 00055 #define ECT_PBOVF 0x02 /* Pulse Accumulator B Overflow Flag */ 00056 00057 /* 00058 * TSCR1 (Timer System Controler Register 1, from pp22) 00059 * bit name normal descr. 00060 * ------------------------------- 00061 * 7 TEN x Timer Enable 00062 * 6 TSWAI 0 Timer Module Stops While in Wait 00063 * 5 TSFRZ 0 Timer and Modulus Counter Stop While in Freeze Mode 00064 * 4 TFFCA 0 Timer Fast Flag Clear All 00065 1 = For TFLG1($0E), a read from an input capture or a write to the 00066 output compare channel ($10 $1F) causes the corresponding channel flag, 00067 CnF, to be cleared. For TFLG2 ($0F), any access to the TCNT register 00068 ($04, $05) clears the TOF flag. Any access to the PACN3 and PACN2 00069 registers ($22, $23) clears the PAOVF and PAIF flags in the PAFLG 00070 register ($21). Any access to the PACN1 and PACN0 registers ($24, $25) 00071 clears the PBOVF flag in the PBFLG register ($31). This has the advantage 00072 of eliminating software overhead in a separate clear sequence. Extra 00073 care is required to avoid accidental flag clearing due to unintended 00074 accesses. 00075 */ 00076 00077 /* 00078 * TSCR2 (Timer System Controler Register 2, from pp25) 00079 * bit name descr. 00080 * ------------------------------- 00081 * 7 TOI Timer Overflow Interrupt Enable (intr on TOF flag set) 00082 * 3 TCRE Timer Counter Reset Enable 00083 This bit allows the timer counter to be 00084 reset by a successful output compare 7 event. This mode of operation is 00085 similar to an up-counting modulus counter. If TC7 = $0000 and TCRE = 1, 00086 TCNT will stay at $0000 continuously. If TC7 = $FFFF and TCRE = 1, 00087 TOF will never be set when TCNT is reset from $FFFF to $0000. 00088 * [2:0] PR2, PR1, PR0 Timer Prescaler Select 00089 These three bits specify the number of /2 stages that are to be inserted between the bus clock and the main timer counter. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 00090 Table 3-4 Prescaler Selection 00091 PR2 PR1 PR0 Prescale Factor 00092 0 0 0 1 00093 0 0 1 2 00094 0 1 0 4 00095 0 1 1 8 00096 1 0 0 16 00097 1 0 1 32 00098 1 1 0 64 00099 1 1 1 128 00100 */ 00101 00102 /* 00103 * TFLG2 (Main Timer Interrupt Flag 2, from pp27) 00104 * bit name descr. 00105 * ------------------------------- 00106 * 7 TOF Timer Overflow Flag 00107 Set when 16-bit free-running timer overflows from $FFFF to $0000. 00108 This bit is cleared automatically by a write to the TFLG2 register with 00109 bit 7 set. (See also TCRE control bit explanation.) 00110 */ 00111 00112 /* 00113 * PACTL (16 bit Pulse Accumulator A, from pp29) 00114 * 16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit pulse 00115 * accumulators PAC3 and PAC2. When PAEN is set, the PACA is enabled. The PACA 00116 * shares the input pin with IC7. 00117 * bit name descr. 00118 * ------------------------------- 00119 * 6 PAEN Pulse Accumulator A System Enable 00120 0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can 00121 be enabled when their related enable bits in ICPAR ($28) are set. 00122 Pulse Accumulator Input Edge Flag (PAIF) function is disabled. 00123 1 = 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse 00124 accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit 00125 pulse accumulator. When PACA in enabled, the PACN3 and PACN2 00126 registers contents are respectively the high and low byte of the 00127 PACA. PA3EN and PA2EN control bits in ICPAR ($28) have no effect. 00128 Pulse Accumulator Input Edge Flag (PAIF) function is enabled. PAEN 00129 is independent from TEN. With timer disabled, the pulse accumulator 00130 can still function unless pulse accumulator is disabled. 00131 * 5 PAMOD Pulse Accumulator Mode 00132 This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). 00133 * 4 PEDGE Pulse Accumulator Edge Control 00134 This bit is active only when the Pulse Accumulator A is enabled 00135 (PAEN = 1). 00136 For PAMOD bit = 0 (event counter mode). 00137 0 = falling edges on PT7 pin cause the count to be incremented 00138 1 = rising edges on PT7 pin cause the count to be incremented 00139 For PAMOD bit = 1 (gated time accumulation mode). 00140 0 = PT7 input pin high enables bus clock divided by 64 to Pulse 00141 Accumulator and the trailing falling edge on PT7 sets the PAIF flag. 00142 1 = PT7 input pin low enables bus clock divided by 64 to Pulse 00143 Accumulator and the trailing rising edge on PT7 sets the PAIF flag 00144 PAMOD PEDGE Pin Action 00145 0 0 Falling edge 00146 0 1 Rising edge 00147 1 0 Div. by 64 clock enabled with pin high level 00148 1 1 Div. by 64 clock enabled with pin low level 00149 Table 3-5 Pin Action If the timer is not active (TEN = 0 in TSCR), 00150 there is no divide-by-64 since the /64 clock is generated by 00151 the timer prescaler. 00152 CLK1, CLK0 Clock Select Bits - Table 3-6 Clock Selection 00153 For the description of PACLK please refer Figure 4-4. If the 00154 pulse accumulator is disabled (PAEN = 0), the prescaler clock 00155 from the timer is always used as an input clock to the timer 00156 counter. The change from one selected clock to the other happens 00157 immediately after these bits are written. 00158 * [3:2] CLK1 CLK0 Clock Source 00159 0 0 Use timer prescaler clock as timer counter clock 00160 0 1 Use PACLK as input to timer counter clock 00161 1 0 Use PACLK/256 as timer counter clock frequency 00162 1 1 Use PACLK/65536 as timer counter clock frequency 00163 * 1 PAOVI Pulse Accumulator A Overflow Interrupt enable. If PAOVF is set 00164 * 0 PAI Pulse Accumulator Input Interrupt enable If PAIF is set 00165 */ 00166 00167 /* 00168 * PAFLG (Pulse Accumulator A Flag Register, from pp31) 00169 * bit name descr. 00170 * ------------------------------- 00171 * 1 PAOVF Pulse Accumulator A Overflow Flag Set when the 16-bit pulse 00172 accumulator A overflows from $FFFF to $0000,or when 8-bit pulse 00173 accumulator 3 (PAC3) overflows from $FF to $00. When PACMX = 1, 00174 PAOVF bit can also be set if 8 - bit pulse accumulator 3 (PAC3) 00175 reaches $FF followed by an active edge on PT3. This bit is 00176 cleared automatically by a write to the PAFLG register with bit 1 set. 00177 * 0 PAIF Pulse Accumulator Input edge Flag Set when the selected edge 00178 is detected at the PT7 input pin. In event mode the event edge 00179 triggers PAIF and in gated time accumulation mode the trailing 00180 edge of the gate signal at the PT7 input pin triggers PAIF. 00181 This bit is cleared by a write to the PAFLG register with bit 0 00182 set. Any access to the PACN3, PACN2 registers will clear all the 00183 flags in this register when TFFCA bit in register TSCR($06) is set. 00184 */ 00185 00186 /* 00187 * MCCTL (16-Bit Modulus Down-Counter Control Register, from pp33) 00188 * bit name descr. 00189 * ------------------------------- 00190 * 7 MCZI Modulus Counter Underflow Interrupt Enable 00191 * 6 MODMC Modulus Mode Enable 0 = The counter counts once from the 00192 value written to it and will stop at $0000. 1 = Modulus mode 00193 is enabled. When the counter reaches $0000, the counter is 00194 loaded with the latest value written to the modulus count 00195 register. NOTE: For proper operation, the MCEN bit should be 00196 cleared before modifying the MODMC bit in order to reset the 00197 modulus counter to $FFFF. 00198 * 5 RDMCL Read Modulus Down-Counter Load 0 = Reads of the modulus 00199 count register will return the present value of the count register. 00200 1 = Reads of the modulus count register will return the contents 00201 of the load register. 00202 * 4 ICLAT Input Capture Force Latch Action When input capture latch 00203 mode is enabled (LATQ and BUFEN bit in ICSYS ($2B) are set, a 00204 write one to this bit immediately forces the contents of the 00205 input capture registers TC0 to TC3 and their corresponding 00206 8-bit pulse accumulators to be latched into the associated 00207 holding registers. The pulse accumulators will be automatically 00208 cleared when the latch action occurs. Writing zero to this bit 00209 has no effect. Read of this bit will return always zero. 00210 * 3 FLMC Force Load Register into the Modulus Counter Count Register 00211 This bit is active only when the modulus down-counter is enabled 00212 (MCEN=1). A write one into this bit loads the load register into 00213 the modulus counter count register. This also resets the modulus 00214 counter prescaler. Write zero to this bit has no effect. When 00215 MODMC=0, counter starts counting and stops at $0000. Read of 00216 this bit will return always zero. 00217 * 2 MCEN Modulus Down-Counter Enable When MCEN=0, the counter is 00218 preset to $FFFF. This will prevent an early interrupt flag when 00219 the modulus down-counter is enabled. 00220 * [1:0] MCPR1, MCPR0 Modulus Counter Prescaler select These two bits 00221 specify the division rate of the modulus counter prescaler. 00222 The newly selected prescaler division rate will not be effective 00223 until a load of the load register into the modulus counter count 00224 register occurs. Table 3-7 Modulus Counter Prescaler Select 00225 MCPR1 MCPR0 Prescaler division rate 00226 0 0 1 00227 0 1 4 00228 1 0 8 00229 1 1 16 00230 */ 00231 00232 /* 00233 * MCFLG (16-Bit Modulus Down-Counter FLAG Register, from pp35) 00234 * bit name descr. 00235 * ------------------------------- 00236 * 7 MCZF Modulus Counter Underflow Flag The flag is set when the modulus 00237 down-counter reaches $0000. A write one to this bit clears the 00238 flag. Write zero has no effect. Any access to the MCCNT register 00239 will clear the MCZF flag in this register when TFFCA bit in register 00240 TSCR($06) is set. 00241 * [3:0] [POLF3:POLF0] First Input Capture Polarity Status This are read 00242 only bits. Write to these bits has no effect. Each status bit 00243 gives the polarity of the first edge which has caused an input 00244 capture to occur after capture latch has been read. Each POLFx 00245 corresponds to a timer PORTx input. 0 = The first input capture 00246 has been caused by a falling edge. 1 = The first input capture 00247 has been caused by a rising edge. 00248 */ 00249 00250 /* 00251 * PBCTL (16-Bit Pulse Accumulator B Control Register, from pp39) 00252 * bit name descr. 00253 * ------------------------------- 00254 * 6 PBEN Pulse Accumulator B System Enable 0 = 16-bit Pulse 00255 Accumulator system disabled. 8-bit PAC1 and PAC0 can be 00256 enabled when their related enable bits in ICPAR ($28) are set. 00257 1 = Pulse Accumulator B system enabled. The two 8-bit pulse 00258 accumulators PAC1 and PAC0 are cascaded to form the PACB 00259 16-bit pulse accumulator. When PACB in enabled, the PACN1 and 00260 PACN0 registers contents are respectively the high and low byte 00261 of the PACB. PA1EN and PA0EN control bits in ICPAR ($28) have 00262 no effect. PBEN is independent from TEN. With timer disabled, 00263 the pulse accumulator can still function unless pulse accumulator 00264 is disabled. 00265 * 1 PBOVI Pulse Accumulator B Overflow Interrupt enable 1 = interrupt 00266 requested if PBOVF is set 00267 */ 00268 00269 /* 00270 * PBFLG (Pulse Accumulator B Flag Register, from pp40) 00271 * bit name descr. 00272 * ------------------------------- 00273 * 2 PBOVF Pulse Accumulator B Overflow Flag This bit is set when 00274 the 16-bit pulse accumulator B overflows from $FFFF to $0000, 00275 or when 8-bit pulse accumulator 1 (PAC1) overflows from $FF to 00276 $00. This bit is cleared by a write to the PBFLG register with 00277 bit 1 set. Any access to the PACN1 and PACN0 registers will 00278 clear the PBOVF flag in this register when TFFCA bit in register 00279 TSCR($06) is set. When PACMX = 1, PBOVF bit can also be set if 00280 8 - bit pulse accumulator 1 (PAC1) reaches $FF and followed 00281 an active edge comes on PT1. 00282 */ 00283 00284 /* Register offsets, derived from pp17. On the 9s12dp256, these are located 00285 * at 0x0040. */ 00286 #define OFF_TIOS 0x00 /* Timer Input Capture/Output Compare Select TIOS Read/Write */ 00287 #define OFF_CFORC 0x01 /* Timer Compare Force Register CFORC Read/Write 1 */ 00288 #define OFF_OC7M 0x02 /* Output Compare 7 Mask Register OC7M Read/Write */ 00289 #define OFF_OC7D 0x03 /* Output Compare 7 Data Register OC7D Read/Write */ 00290 #define OFF_TCNT_H 0x04 /* Timer Count Register High TCNT Read/Write 2 */ 00291 #define OFF_TCNT_L 0x05 /* Timer Count Register Low TCNT Read/Write 2 */ 00292 #define OFF_TSCR1 0x06 /* Timer System Control Register1 TSCR1 Read/Write */ 00293 #define OFF_TTOV 0x07 /* Timer Toggle Overflow Register TTOV Read/Write */ 00294 #define OFF_TCTL1 0x08 /* Timer Control Register1 TCTL1 Read/Write */ 00295 #define OFF_TCTL2 0x09 /* Timer Control Register2 TCTL2 Read/Write */ 00296 #define OFF_TCTL3 0x0A /* Timer Control Register3 TCTL3 Read/Write */ 00297 #define OFF_TCTL4 0x0B /* Timer Control Register4 TCTL4 Read/Write */ 00298 #define OFF_TIE 0x0C /* Timer Interrupt Enable Register TIE Read/Write */ 00299 #define OFF_TSCR2 0x0D /* Timer System Control Register2 TSCR2 Read/Write */ 00300 #define OFF_TFLG1 0x0E /* Main Timer Interrupt Flag1 TFLG1 Read/Write */ 00301 #define OFF_TFLG2 0x0F /* Main Timer Interrupt Flag2 TFLG2 Read/Write */ 00302 #define OFF_TC0_H 0x10 /* (TC0) Read/Write 3 */ 00303 #define OFF_TC0_L 0x11 /* (TC0) Read/Write 3 */ 00304 #define OFF_TC1_H 0x12 /* (TC1) Read/Write 3 */ 00305 #define OFF_TC1_L 0x13 /* (TC1) Read/Write 3 */ 00306 #define OFF_TC2_H 0x14 /* (TC2) Read/Write 3 */ 00307 #define OFF_TC2_L 0x15 /* (TC2) Read/Write 3 */ 00308 #define OFF_TC3_H 0x16 /* (TC3) Read/Write 3 */ 00309 #define OFF_TC3_L 0x17 /* (TC3) Read/Write 3 */ 00310 #define OFF_TC4_H 0x18 /* (TC4) Read/Write 3 */ 00311 #define OFF_TC4_L 0x19 /* (TC4) Read/Write 3 */ 00312 #define OFF_TC5_H 0x1A /* (TC5) Read/Write 3 */ 00313 #define OFF_TC5_L 0x1B /* (TC5) Read/Write 3 */ 00314 #define OFF_TC6_H 0x1C /* (TC6) Read/Write 3 */ 00315 #define OFF_TC6_L 0x1D /* (TC6) Read/Write 3 */ 00316 #define OFF_TC7_H 0x1E /* (TC7) Read/Write 3 */ 00317 #define OFF_TC7_L 0x1F /* (TC7) Read/Write 3 */ 00318 #define OFF_PACTL 0x20 /* 16Bit Pulse Accumulator A Control Register (PACTL) Read/Write */ 00319 #define OFF_PAFLG 0x21 /* Pulse Accumulator A Flag Register PAFLG Read/Write */ 00320 #define OFF_PACN3 0x22 /* Pulse Accumulator Count Register3 PACN3 Read/Write */ 00321 #define OFF_PACN2 0x23 /* Pulse Accumulator Count Register2 PACN2 Read/Write */ 00322 #define OFF_PACN1 0x24 /* Pulse Accumulator Count Register1 PACN1 Read/Write */ 00323 #define OFF_PACN0 0x25 /* Pulse Accumulator Count Register0 PACN0 Read/Write */ 00324 #define OFF_MCCTL 0x26 /* 16Bit Modulus Down Counter Register MCCTL Read/Write */ 00325 #define OFF_MCFLG 0x27 /* 16Bit Modulus Down Counter Flag Register (MCFLG) Read/Write */ 00326 #define OFF_ICPAR 0x28 /* Input Control Pulse Accumulator Register ICPAR Read/Write */ 00327 #define OFF_DLYCT 0x29 /* Delay Counter Control Register DLYCT Read/Write */ 00328 #define OFF_ICOVW 0x2A /* Input Control Overwrite Register ICOVW Read/Write */ 00329 #define OFF_ICSYS 0x2B /* Input Control System Control Register ICSYS Read/Write 4 */ 00330 /* $_2C Reserved */ 00331 #define OFF_TIMTST 0x2D /* Timer Test Register TIMTST Read/Write 2 */ 00332 /* $_2E Reserved */ 00333 /* $_2F Reserved */ 00334 #define OFF_PBCTL 0x30 /* 16Bit Pulse Accumulator B Control Register (PBCTL) Read/Write */ 00335 #define OFF_PBFLG 0x31 /* 16Bit Pulse Accumulator B Flag Register PBFLG Read/Write */ 00336 #define OFF_PA3H 0x32 /* 8Bit Pulse Accumulator Holding Register3 PA3H Read/Write 5 */ 00337 #define OFF_PA2H 0x33 /* 8Bit Pulse Accumulator Holding Register2 PA2H Read/Write 5 */ 00338 #define OFF_PA1H 0x34 /* 8Bit Pulse Accumulator Holding Register1 PA1H Read/Write 5 */ 00339 #define OFF_PA0H 0x35 /* 8Bit Pulse Accumulator Holding Register0 PA0H Read/Write 5 */ 00340 #define OFF_MCCNT_H 0x36 /* Modulus DownCounter Count Register High (MCCNT) Read/Write */ 00341 #define OFF_MCCNT_L 0x37 /* Modulus DownCounter Count Register Low */ 00342 #define OFF_TC0H_H 0x38 /* Timer Input Capture Holding Register0 High TC0H Read/Write 5 */ 00343 #define OFF_TC0H_L 0x39 /* Timer Input Capture Holding Register0 Low TC0H Read/Write 5 */ 00344 #define OFF_TC1H_H 0x3A /* Timer Input Capture Holding Register1 HighTC1H Read/Write 5 */ 00345 #define OFF_TC1H_L 0x3B /* Timer Input Capture Holding Register1 Low TC1H Read/Write 5 */ 00346 #define OFF_TC2H_H 0x3C /* Timer Input Capture Holding Register2 High TC2H Read/Write 5 */ 00347 #define OFF_TC2H_L 0x3D /* Timer Input Capture Holding Register2 Low TC2H Read/Write 5 */ 00348 #define OFF_TC3H_H 0x3E /* Timer Input Capture Holding Register3 High TC3H Read/Write 5 */ 00349 #define OFF_TC3H_L 0x3F /* Timer Input Capture Holding Register3 Low TC3H Read/Write 5 */
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