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Defines |
| #define | TCNT_CLK 64 /* TCNT rate is 64us, check ect_init. */ |
| #define | MSEC2TCNT(ms) ((ms*1000) / TCNT_CLK) |
| #define | ECT_TEN 0x80 /* Timer Enable */ |
| #define | ECT_TSWAI 0x40 /* Timer Module Stops While in Wait */ |
| #define | ECT_TSFRZ 0x20 /* Timer and Modulus Counter Stop While in Freeze Mode */ |
| #define | ECT_TFFCA 0x10 /* Timer Fast Flag Clear All */ |
| #define | ECT_TOI 0x80 /* Timer Overflow Interrupt Enable (intr on TOF flag set) */ |
| #define | ECT_TCRE 0x08 /* Timer Counter Reset Enable */ |
| #define | ECT_PR2 0x04 /* PR2, PR1, PR0 Timer Prescaler Select */ |
| #define | ECT_PR1 0x02 /* PR2, PR1, PR0 Timer Prescaler Select */ |
| #define | ECT_PR0 0x01 /* PR2, PR1, PR0 Timer Prescaler Select */ |
| #define | ECT_TOF 0x80 /* Timer Overflow Flag */ |
| #define | ECT_PAEN 0x40 /* Pulse Accumulator A System Enable */ |
| #define | ECT_PAMOD 0x20 /* Pulse Accumulator Mode */ |
| #define | ECT_PEDGE 0x10 /* Pulse Accumulator Edge Control */ |
| #define | ECT_CLK1 0X08 /* CLK1 CLK0 Clock Source */ |
| #define | ECT_CLK2 0x04 /* CLK1 CLK0 Clock Source */ |
| #define | ECT_PAOVI 0x02 /* Pulse Accumulator A Overflow Interrupt enable */ |
| #define | ECT_PAI 0x01 /* Pulse Accumulator Input Interrupt enable */ |
| #define | ECT_PAOVF 0x02 /* Pulse Accumulator A Overflow Flag */ |
| #define | ECT_PAIF 0x01 /* Pulse Accumulator Input edge Flag */ |
| #define | ECT_MCCTL 0x80 /* Modulus Counter Underflow Interrupt Enable */ |
| #define | ECT_MODMC 0x40 /* Modulus Mode Enable */ |
| #define | ECT_RDMCL 0x20 /* Read Modulus Down-Counter Load */ |
| #define | ECT_ICLAT 0x10 /* Input Capture Force Latch Action */ |
| #define | ECT_FLMC 0x08 /* Force Load Register into the Modulus Counter Count Register */ |
| #define | ECT_MCEN 0x04 /* Modulus Down-Counter Enable */ |
| #define | ECT_MCPR1 0x02 /* MCPR1, MCPR0 Modulus Counter Prescaler select */ |
| #define | ECT_MCPR0 0x01 /* MCPR1, MCPR0 Modulus Counter Prescaler select */ |
| #define | ECT_MCZF 0x80 /* Modulus Counter Underflow Flag */ |
| #define | ECT_PBEN 0x40 /* Pulse Accumulator B System Enable */ |
| #define | ECT_PBOVI 0x02 /* Pulse Accumulator B Overflow Interrupt enable */ |
| #define | ECT_PBOVF 0x02 /* Pulse Accumulator B Overflow Flag */ |
| #define | OFF_TIOS 0x00 /* Timer Input Capture/Output Compare Select TIOS Read/Write */ |
| #define | OFF_CFORC 0x01 /* Timer Compare Force Register CFORC Read/Write 1 */ |
| #define | OFF_OC7M 0x02 /* Output Compare 7 Mask Register OC7M Read/Write */ |
| #define | OFF_OC7D 0x03 /* Output Compare 7 Data Register OC7D Read/Write */ |
| #define | OFF_TCNT_H 0x04 /* Timer Count Register High TCNT Read/Write 2 */ |
| #define | OFF_TCNT_L 0x05 /* Timer Count Register Low TCNT Read/Write 2 */ |
| #define | OFF_TSCR1 0x06 /* Timer System Control Register1 TSCR1 Read/Write */ |
| #define | OFF_TTOV 0x07 /* Timer Toggle Overflow Register TTOV Read/Write */ |
| #define | OFF_TCTL1 0x08 /* Timer Control Register1 TCTL1 Read/Write */ |
| #define | OFF_TCTL2 0x09 /* Timer Control Register2 TCTL2 Read/Write */ |
| #define | OFF_TCTL3 0x0A /* Timer Control Register3 TCTL3 Read/Write */ |
| #define | OFF_TCTL4 0x0B /* Timer Control Register4 TCTL4 Read/Write */ |
| #define | OFF_TIE 0x0C /* Timer Interrupt Enable Register TIE Read/Write */ |
| #define | OFF_TSCR2 0x0D /* Timer System Control Register2 TSCR2 Read/Write */ |
| #define | OFF_TFLG1 0x0E /* Main Timer Interrupt Flag1 TFLG1 Read/Write */ |
| #define | OFF_TFLG2 0x0F /* Main Timer Interrupt Flag2 TFLG2 Read/Write */ |
| #define | OFF_TC0_H 0x10 /* (TC0) Read/Write 3 */ |
| #define | OFF_TC0_L 0x11 /* (TC0) Read/Write 3 */ |
| #define | OFF_TC1_H 0x12 /* (TC1) Read/Write 3 */ |
| #define | OFF_TC1_L 0x13 /* (TC1) Read/Write 3 */ |
| #define | OFF_TC2_H 0x14 /* (TC2) Read/Write 3 */ |
| #define | OFF_TC2_L 0x15 /* (TC2) Read/Write 3 */ |
| #define | OFF_TC3_H 0x16 /* (TC3) Read/Write 3 */ |
| #define | OFF_TC3_L 0x17 /* (TC3) Read/Write 3 */ |
| #define | OFF_TC4_H 0x18 /* (TC4) Read/Write 3 */ |
| #define | OFF_TC4_L 0x19 /* (TC4) Read/Write 3 */ |
| #define | OFF_TC5_H 0x1A /* (TC5) Read/Write 3 */ |
| #define | OFF_TC5_L 0x1B /* (TC5) Read/Write 3 */ |
| #define | OFF_TC6_H 0x1C /* (TC6) Read/Write 3 */ |
| #define | OFF_TC6_L 0x1D /* (TC6) Read/Write 3 */ |
| #define | OFF_TC7_H 0x1E /* (TC7) Read/Write 3 */ |
| #define | OFF_TC7_L 0x1F /* (TC7) Read/Write 3 */ |
| #define | OFF_PACTL 0x20 /* 16Bit Pulse Accumulator A Control Register (PACTL) Read/Write */ |
| #define | OFF_PAFLG 0x21 /* Pulse Accumulator A Flag Register PAFLG Read/Write */ |
| #define | OFF_PACN3 0x22 /* Pulse Accumulator Count Register3 PACN3 Read/Write */ |
| #define | OFF_PACN2 0x23 /* Pulse Accumulator Count Register2 PACN2 Read/Write */ |
| #define | OFF_PACN1 0x24 /* Pulse Accumulator Count Register1 PACN1 Read/Write */ |
| #define | OFF_PACN0 0x25 /* Pulse Accumulator Count Register0 PACN0 Read/Write */ |
| #define | OFF_MCCTL 0x26 /* 16Bit Modulus Down Counter Register MCCTL Read/Write */ |
| #define | OFF_MCFLG 0x27 /* 16Bit Modulus Down Counter Flag Register (MCFLG) Read/Write */ |
| #define | OFF_ICPAR 0x28 /* Input Control Pulse Accumulator Register ICPAR Read/Write */ |
| #define | OFF_DLYCT 0x29 /* Delay Counter Control Register DLYCT Read/Write */ |
| #define | OFF_ICOVW 0x2A /* Input Control Overwrite Register ICOVW Read/Write */ |
| #define | OFF_ICSYS 0x2B /* Input Control System Control Register ICSYS Read/Write 4 */ |
| #define | OFF_TIMTST 0x2D /* Timer Test Register TIMTST Read/Write 2 */ |
| #define | OFF_PBCTL 0x30 /* 16Bit Pulse Accumulator B Control Register (PBCTL) Read/Write */ |
| #define | OFF_PBFLG 0x31 /* 16Bit Pulse Accumulator B Flag Register PBFLG Read/Write */ |
| #define | OFF_PA3H 0x32 /* 8Bit Pulse Accumulator Holding Register3 PA3H Read/Write 5 */ |
| #define | OFF_PA2H 0x33 /* 8Bit Pulse Accumulator Holding Register2 PA2H Read/Write 5 */ |
| #define | OFF_PA1H 0x34 /* 8Bit Pulse Accumulator Holding Register1 PA1H Read/Write 5 */ |
| #define | OFF_PA0H 0x35 /* 8Bit Pulse Accumulator Holding Register0 PA0H Read/Write 5 */ |
| #define | OFF_MCCNT_H 0x36 /* Modulus DownCounter Count Register High (MCCNT) Read/Write */ |
| #define | OFF_MCCNT_L 0x37 /* Modulus DownCounter Count Register Low */ |
| #define | OFF_TC0H_H 0x38 /* Timer Input Capture Holding Register0 High TC0H Read/Write 5 */ |
| #define | OFF_TC0H_L 0x39 /* Timer Input Capture Holding Register0 Low TC0H Read/Write 5 */ |
| #define | OFF_TC1H_H 0x3A /* Timer Input Capture Holding Register1 HighTC1H Read/Write 5 */ |
| #define | OFF_TC1H_L 0x3B /* Timer Input Capture Holding Register1 Low TC1H Read/Write 5 */ |
| #define | OFF_TC2H_H 0x3C /* Timer Input Capture Holding Register2 High TC2H Read/Write 5 */ |
| #define | OFF_TC2H_L 0x3D /* Timer Input Capture Holding Register2 Low TC2H Read/Write 5 */ |
| #define | OFF_TC3H_H 0x3E /* Timer Input Capture Holding Register3 High TC3H Read/Write 5 */ |
| #define | OFF_TC3H_L 0x3F /* Timer Input Capture Holding Register3 Low TC3H Read/Write 5 */ |
Functions |
| __inline__ void | ect_init (void) |
1.3.6-20040222