00001 00009 /* Generated for the BeeOS project 2004/03 by Paul Harvey, 00010 * csirac@users.sourceforge.net. 00011 */ 00012 00013 #define SCI0BDH SC0BDH /* SCI 0 Baud Rate Control Register High pp294 bits: BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 Reset: 0 0 0 0 0 0 0 0 */ 00014 #define SCI0BDL SC0BDL /* SCI 0 Baud Rate Control Register Low pp294 bits: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Reset: 0 0 0 0 0 1 0 0 */ 00015 #define SCI0CR1 SC0CR1 /* SCI Control Register 1 pp295 bits: LOOPS WOMS RSRC M WAKE ILT PE PT Reset: 0 0 0 0 0 0 0 0 */ 00016 #define SCI0CR2 SC0CR2 /* SCI Control Register 2 pp298 bits: TIE TCIE RIE ILIE TE RE RWU SBK Reset: 0 0 0 0 0 0 0 0 */ 00017 #define SCI0SR1 SC0SR1 /* SCI Status Register 1 pp299 bits: TDRE TC RDRF IDLE OR NF FE PF Reset: 1 1 0 0 0 0 0 0 */ 00018 #define SCI0SR2 SC0SR2 /* SCI Status Register 2 pp301 bits: 0 0 0 0 0 0 0 RAF Reset: 0 0 0 0 0 0 0 0 */ 00019 #define SCI0DRH SC0DRH /* SCI Data Register High pp302 bits: R8 T8 0 0 0 0 0 0 Reset: U U 0 0 0 0 0 0 */ 00020 #define SCI0DRL SC0DRL /* SCI Data Register Low pp302 bits: R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Reset: Unaffected by reset */
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