ports_std.h File Reference

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Detailed Description

Standard naming substitutions for ports & registers.

Substitutes names derived directly from datasheet (which vary from chip to chip) into a consistent naming scheme chosen for BeeOS (9s12dp256 naming).

Note:

The different naming may imply different usage; TODO: check out differences.

See also:

asm-m68hc12b/ports.h

Definition in file m68hc12b/ports_std.h.

Go to the source code of this file.

Defines
#define	SCI0BDH   SC0BDH /* SCI 0 Baud Rate Control Register High pp294 bits: BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 Reset: 0 0 0 0 0 0 0 0 */
#define	SCI0BDL   SC0BDL /* SCI 0 Baud Rate Control Register Low pp294 bits: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Reset: 0 0 0 0 0 1 0 0 */
#define	SCI0CR1   SC0CR1 /* SCI Control Register 1 pp295 bits: LOOPS WOMS RSRC M WAKE ILT PE PT Reset: 0 0 0 0 0 0 0 0 */
#define	SCI0CR2   SC0CR2 /* SCI Control Register 2 pp298 bits: TIE TCIE RIE ILIE TE RE RWU SBK Reset: 0 0 0 0 0 0 0 0 */
#define	SCI0SR1   SC0SR1 /* SCI Status Register 1 pp299 bits: TDRE TC RDRF IDLE OR NF FE PF Reset: 1 1 0 0 0 0 0 0 */
#define	SCI0SR2   SC0SR2 /* SCI Status Register 2 pp301 bits: 0 0 0 0 0 0 0 RAF Reset: 0 0 0 0 0 0 0 0 */
#define	SCI0DRH   SC0DRH /* SCI Data Register High pp302 bits: R8 T8 0 0 0 0 0 0 Reset: U U 0 0 0 0 0 0 */
#define	SCI0DRL   SC0DRL /* SCI Data Register Low pp302 bits: R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Reset: Unaffected by reset */

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Define Documentation

#define SCI0BDH   SC0BDH /* SCI 0 Baud Rate Control Register High pp294 bits: BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 Reset: 0 0 0 0 0 0 0 0 */

Definition at line 13 of file m68hc12b/ports_std.h.

#define SCI0BDL   SC0BDL /* SCI 0 Baud Rate Control Register Low pp294 bits: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Reset: 0 0 0 0 0 1 0 0 */

Definition at line 15 of file m68hc12b/ports_std.h.

#define SCI0CR1   SC0CR1 /* SCI Control Register 1 pp295 bits: LOOPS WOMS RSRC M WAKE ILT PE PT Reset: 0 0 0 0 0 0 0 0 */

Definition at line 17 of file m68hc12b/ports_std.h.

#define SCI0CR2   SC0CR2 /* SCI Control Register 2 pp298 bits: TIE TCIE RIE ILIE TE RE RWU SBK Reset: 0 0 0 0 0 0 0 0 */

Definition at line 19 of file m68hc12b/ports_std.h.

#define SCI0DRH   SC0DRH /* SCI Data Register High pp302 bits: R8 T8 0 0 0 0 0 0 Reset: U U 0 0 0 0 0 0 */

Definition at line 25 of file m68hc12b/ports_std.h.

#define SCI0DRL   SC0DRL /* SCI Data Register Low pp302 bits: R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Reset: Unaffected by reset */

Definition at line 27 of file m68hc12b/ports_std.h.

#define SCI0SR1   SC0SR1 /* SCI Status Register 1 pp299 bits: TDRE TC RDRF IDLE OR NF FE PF Reset: 1 1 0 0 0 0 0 0 */

Definition at line 21 of file m68hc12b/ports_std.h.

#define SCI0SR2   SC0SR2 /* SCI Status Register 2 pp301 bits: 0 0 0 0 0 0 0 RAF Reset: 0 0 0 0 0 0 0 0 */

Definition at line 23 of file m68hc12b/ports_std.h.

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