sci.c

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/* BeeOS v0.1. Created: 2004/03/21 Modified: 2004/03/21
 * Copyright (C) 2004 Paul Harvey - ROMA, Australia.
 * csirac@users.sourceforge.net
 */

/*   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 * 
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 * 
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "../include/beeos.h"
#ifndef HOSTED_BUILD
#   include "../include/asm/ports.h"
#   include "../include/asm/ports_std.h"
#   include "../include/arch/param.h"
#   define IN_SCI
#   include "../include/sci.h"

#   ifdef SCI0
    extern void sci0_init(ushort baud)
    {
        ushort t = (ushort) ( ((long int)(CPU_CLOCK / 10L / 16L)) / (long int) baud);
        
        ASM_MOVW_MM(t, SCI0BDH);
        /* IREN, TNP[1:0] should be zero as long as baud is not an illegal value, */
        SCI0BDH = SCI0BDH &~SCI_IREN &~SCI_TNP1 &~SCI_TNP0; /* but clear anyway */
        SCI0CR1 = 0x00; /* No parity, 8bits data */
        SCI0CR2 = 0x00 | SCI_RE | SCI_TE;   /* Enable TX & RX */
        if (SCI0SR1) SCI0DRH = 0x00;    /* Clear TDRE: read from SCIDR */
        TOUSHORT(SCI0DRH) = 0x00;                   /* and write to it */
        SCI0SR2 = 0x00; /* BRK char = 10/13bits, Single wire mode = TX in, etc */
        DDRS |= 0x03;   /* DDR, etc. are overridden when SCI is enabled, but */
        PERS |= 0X03;   /* if WOMS is set, need internal pullups (overridden */
        PPSS &= ~0x03;  /* if WOMS isn't set). */
        
        return;
    }
#   endif
    
#   ifdef SCI1
    extern void sci1_init(ushort baud)
    {
        /* IREN, TNP[1:0] should be zero as long as baud is not an illegal value. */
        TOUSHORT(SCI1BDH) = ( ((ushort)(CPU_CLOCK / 16L)) / baud);
        SCI1BDH = SCI0BDH &~SCI_IREN &~SCI_TNP1 &~SCI_TNP0;
        SCI1CR1 = 0x00; /* No parity, 8bits data */
        SCI1CR2 = 0x00 | SCI_RE | SCI_TE;   /* Enable TX & RX */
        if (SCI1SR1) SCI1DRH = 0x00;*/  /* Clear TDRE: read from SCIDR */
        SCI1DRH = 0;                    /* and write to it */
        SCI1SR2 = 0x00; /* BRK char = 10/13bits, Single wire mode = TX in, etc */
        
        return;
    }
#   endif
    
#   if 0
    extern char sci_rx_poll(unsigned char *sci_base)
    {   
        return sci_base[SCISR1] & SCI_RDRF;
    }
    
    extern void sci_tx_flush(unsigned char *sci_base)
    {   
        while (!(sci_base[SCISR1] & SCI_TDRE)) ;
        
        return;
    }
#   endif 
    
    extern void sci_tx(unsigned char *sci_base, char data)
    {   
    /* Why oh why... while (!(sci_base[SCISR1] & SCI_TDRE)); does not work. After 2
     * hours on the simulator, reading compiler ASM output, stepping, tracing...
     * GCC simply will not produce code that reads from SR1 properly.
     * Hence the asm.
     */
        /*
            while (!(sci_base[SCISR1] & SCI_TDRE)); ;;tx_flush()
            sci_base[SCIDRL] = data;
        */
        __asm__ __volatile__ ( 
            "sci_tx_hack:\
            \n\tldaa %1         ;; SCI_TDRE bit\
            \n\tanda %0         ;; AND w/SCISR1\
            \n\tbeq sci_tx_hack ;; If bit is zero, keep looping\
            \n\tmovb %3, %2     ;; Write next byte into TX shift register"
            :                                               /* Output */
            : "m" (sci_base[SCISR1]), "n" (SCI_TDRE),       /* Input */
                "m" (sci_base[SCIDRL]), "m" (data)
            : "%a", "%ccr"                                  /* Clobbered */
        );
        
        return;
    }
    
    extern char sci_rx(unsigned char *sci_base, char data)
    {   
        while (!(sci_base[SCISR1] & SCI_RDRF));
        
        return (char) sci_base[SCIDRL];
    }
#endif

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