Based on information provided in S12SCIV3.pdf by Motorola, Inc. v03.02.
Definition in file sci.c.
#include "../include/beeos.h"
#include "../include/asm/ports.h"
#include "../include/asm/ports_std.h"
#include "../include/arch/param.h"
#include "../include/sci.h"
Include dependency graph for sci.c:
Go to the source code of this file.
Defines | |
#define | IN_SCI |
Functions | |
void | sci0_init (ushort baud) |
void | sci_tx (unsigned char *sci_base, char data) |
char | sci_rx (unsigned char *sci_base, char data) |
TX a byte of data; wait for in-progress transmission to finish first. |
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Definition at line 35 of file sci.c. References ASM_MOVW_MM, CPU_CLOCK, DDRS, PERS, PPSS, SCI0BDH, SCI0CR1, SCI0CR2, SCI0DRH, SCI0SR1, SCI0SR2, SCI_IREN, SCI_RE, SCI_TE, SCI_TNP0, SCI_TNP1, TOUSHORT, and ushort.
00036 { 00041 ushort t = (ushort) ( ((long int)(CPU_CLOCK / 10L / 16L)) / (long int) baud); 00042 00043 ASM_MOVW_MM(t, SCI0BDH); 00044 /* IREN, TNP[1:0] should be zero as long as baud is not an illegal value, */ 00045 SCI0BDH = SCI0BDH &~SCI_IREN &~SCI_TNP1 &~SCI_TNP0; /* but clear anyway */ 00046 SCI0CR1 = 0x00; /* No parity, 8bits data */ 00047 SCI0CR2 = 0x00 | SCI_RE | SCI_TE; /* Enable TX & RX */ 00048 if (SCI0SR1) SCI0DRH = 0x00; /* Clear TDRE: read from SCIDR */ 00049 TOUSHORT(SCI0DRH) = 0x00; /* and write to it */ 00050 SCI0SR2 = 0x00; /* BRK char = 10/13bits, Single wire mode = TX in, etc */ 00051 DDRS |= 0x03; /* DDR, etc. are overridden when SCI is enabled, but */ 00052 PERS |= 0X03; /* if WOMS is set, need internal pullups (overridden */ 00053 PPSS &= ~0x03; /* if WOMS isn't set). */ 00054 00055 return; 00056 } |
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TX a byte of data; wait for in-progress transmission to finish first.
Definition at line 128 of file sci.c. References SCI_RDRF, SCIDRL, and SCISR1.
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Definition at line 95 of file sci.c. References __asm__(), SCI_TDRE, SCIDRL, and SCISR1. Referenced by putchar().
00096 { 00104 /* Why oh why... while (!(sci_base[SCISR1] & SCI_TDRE)); does not work. After 2 00105 * hours on the simulator, reading compiler ASM output, stepping, tracing... 00106 * GCC simply will not produce code that reads from SR1 properly. 00107 * Hence the asm. 00108 */ 00109 /* 00110 while (!(sci_base[SCISR1] & SCI_TDRE)); ;;tx_flush() 00111 sci_base[SCIDRL] = data; 00112 */ 00113 __asm__ __volatile__ ( 00114 "sci_tx_hack:\ 00115 \n\tldaa %1 ;; SCI_TDRE bit\ 00116 \n\tanda %0 ;; AND w/SCISR1\ 00117 \n\tbeq sci_tx_hack ;; If bit is zero, keep looping\ 00118 \n\tmovb %3, %2 ;; Write next byte into TX shift register" 00119 : /* Output */ 00120 : "m" (sci_base[SCISR1]), "n" (SCI_TDRE), /* Input */ 00121 "m" (sci_base[SCIDRL]), "m" (data) 00122 : "%a", "%ccr" /* Clobbered */ 00123 ); 00124 00125 return; 00126 } |
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